drivers/clk/samsung/clk-exynos5260.c

Source file repositories/reference/linux-study-clean/drivers/clk/samsung/clk-exynos5260.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/samsung/clk-exynos5260.c
Extension
.c
Size
65646 bytes
Lines
1853
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 * Author: Rahul Sharma <rahul.sharma@samsung.com>
 *
 * Common Clock Framework support for Exynos5260 SoC.
 */

#include "clk-exynos5260.h"
#include "clk.h"
#include "clk-pll.h"

#include <dt-bindings/clock/exynos5260-clk.h>

/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP			(PHYCLK_USBDRD30_UDRD30_PHYCLOCK + 1)
#define CLKS_NR_EGL			(EGL_DOUT_EGL1 + 1)
#define CLKS_NR_KFC			(KFC_DOUT_KFC1 + 1)
#define CLKS_NR_MIF			(MIF_SCLK_LPDDR3PHY_WRAP_U0 + 1)
#define CLKS_NR_G3D			(G3D_CLK_G3D + 1)
#define CLKS_NR_AUD			(AUD_SCLK_I2S + 1)
#define CLKS_NR_MFC			(MFC_CLK_SMMU2_MFCM0 + 1)
#define CLKS_NR_GSCL			(GSCL_SCLK_CSIS0_WRAP + 1)
#define CLKS_NR_FSYS			(FSYS_PHYCLK_USBHOST20 + 1)
#define CLKS_NR_PERI			(PERI_SCLK_PCM1 + 1)
#define CLKS_NR_DISP			(DISP_MOUT_HDMI_PHY_PIXEL_USER + 1)
#define CLKS_NR_G2D			(G2D_CLK_SMMU3_G2D + 1)
#define CLKS_NR_ISP			(ISP_SCLK_UART_EXT + 1)

/*
 * Applicable for all 2550 Type PLLS for Exynos5260, listed below
 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
 */
static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = {
	PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
	PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
	PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
	PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
	PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
	PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
	PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
	PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
	PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
	PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
	PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
	PLL_35XX_RATE(24 * MHZ, 733000000, 733, 12, 1),
	PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
	PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
	PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
	PLL_35XX_RATE(24 * MHZ, 620000000, 310, 3, 2),
	PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
	PLL_35XX_RATE(24 * MHZ, 543000000, 362, 4, 2),
	PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),
	PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
	PLL_35XX_RATE(24 * MHZ, 450000000, 300, 4, 2),
	PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
	PLL_35XX_RATE(24 * MHZ, 350000000, 175, 3, 2),
	PLL_35XX_RATE(24 * MHZ, 300000000, 400, 4, 3),
	PLL_35XX_RATE(24 * MHZ, 266000000, 266, 3, 3),
	PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
	PLL_35XX_RATE(24 * MHZ, 160000000, 160, 3, 3),
};

/*
 * Applicable for 2650 Type PLL for AUD_PLL.
 */
static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = {
	PLL_36XX_RATE(24 * MHZ, 1600000000, 200, 3, 0, 0),
	PLL_36XX_RATE(24 * MHZ, 1200000000, 100, 2, 0, 0),
	PLL_36XX_RATE(24 * MHZ, 1000000000, 250, 3, 1, 0),
	PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
	PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
	PLL_36XX_RATE(24 * MHZ, 532000000, 266, 3, 2, 0),
	PLL_36XX_RATE(24 * MHZ, 480000000, 160, 2, 2, 0),
	PLL_36XX_RATE(24 * MHZ, 432000000, 144, 2, 2, 0),
	PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
	PLL_36XX_RATE(24 * MHZ, 394073128, 459, 7, 2, 49282),
	PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),
	PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),
	PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
	PLL_36XX_RATE(24 * MHZ, 200000000, 200, 3, 3, 0),
	PLL_36XX_RATE(24 * MHZ, 166000000, 166, 3, 3, 0),
	PLL_36XX_RATE(24 * MHZ, 133000000, 266, 3, 4, 0),
	PLL_36XX_RATE(24 * MHZ, 100000000, 200, 3, 4, 0),
	PLL_36XX_RATE(24 * MHZ, 66000000, 176, 2, 5, 0),
};

/* CMU_AUD */

static const unsigned long aud_clk_regs[] __initconst = {

Annotation

Implementation Notes