drivers/clk/samsung/clk-s3c64xx.c

Source file repositories/reference/linux-study-clean/drivers/clk/samsung/clk-s3c64xx.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/samsung/clk-s3c64xx.c
Extension
.c
Size
19418 bytes
Lines
480
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
 *
 * Common Clock Framework support for all S3C64xx SoCs.
 */

#include <linux/slab.h>
#include <linux/clk-provider.h>
#include <linux/clk/samsung.h>
#include <linux/of_address.h>

#include <dt-bindings/clock/samsung,s3c64xx-clock.h>

#include "clk.h"
#include "clk-pll.h"

/* S3C64xx clock controller register offsets. */
#define APLL_LOCK		0x000
#define MPLL_LOCK		0x004
#define EPLL_LOCK		0x008
#define APLL_CON		0x00c
#define MPLL_CON		0x010
#define EPLL_CON0		0x014
#define EPLL_CON1		0x018
#define CLK_SRC			0x01c
#define CLK_DIV0		0x020
#define CLK_DIV1		0x024
#define CLK_DIV2		0x028
#define HCLK_GATE		0x030
#define PCLK_GATE		0x034
#define SCLK_GATE		0x038
#define MEM0_GATE		0x03c
#define CLK_SRC2		0x10c
#define OTHERS			0x900

/* Helper macros to define clock arrays. */
#define FIXED_RATE_CLOCKS(name)	\
		static struct samsung_fixed_rate_clock name[]
#define MUX_CLOCKS(name)	\
		static struct samsung_mux_clock name[]
#define DIV_CLOCKS(name)	\
		static struct samsung_div_clock name[]
#define GATE_CLOCKS(name)	\
		static struct samsung_gate_clock name[]

/* Helper macros for gate types present on S3C64xx. */
#define GATE_BUS(_id, cname, pname, o, b) \
		GATE(_id, cname, pname, o, b, 0, 0)
#define GATE_SCLK(_id, cname, pname, o, b) \
		GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
#define GATE_ON(_id, cname, pname, o, b) \
		GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)

static void __iomem *reg_base;
static bool is_s3c6400;

/*
 * List of controller registers to be saved and restored during
 * a suspend/resume cycle.
 */
static unsigned long s3c64xx_clk_regs[] __initdata = {
	APLL_LOCK,
	MPLL_LOCK,
	EPLL_LOCK,
	APLL_CON,
	MPLL_CON,
	EPLL_CON0,
	EPLL_CON1,
	CLK_SRC,
	CLK_DIV0,
	CLK_DIV1,
	CLK_DIV2,
	HCLK_GATE,
	PCLK_GATE,
	SCLK_GATE,
};

static unsigned long s3c6410_clk_regs[] __initdata = {
	CLK_SRC2,
	MEM0_GATE,
};

/* List of parent clocks common for all S3C64xx SoCs. */
PNAME(spi_mmc_p)	= { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
PNAME(uart_p)		= { "mout_epll", "dout_mpll" };
PNAME(audio0_p)		= { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
				"pcmcdclk0", "none", "none", "none" };
PNAME(audio1_p)		= { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
				"pcmcdclk0", "none", "none", "none" };

Annotation

Implementation Notes