drivers/clk/samsung/clk-s5pv210.c

Source file repositories/reference/linux-study-clean/drivers/clk/samsung/clk-s5pv210.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/samsung/clk-s5pv210.c
Extension
.c
Size
26541 bytes
Lines
818
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
 *
 * Based on clock drivers for S3C64xx and Exynos4 SoCs.
 *
 * Common Clock Framework support for all S5PC110/S5PV210 SoCs.
 */

#include <linux/clk-provider.h>
#include <linux/of_address.h>

#include "clk.h"
#include "clk-pll.h"

#include <dt-bindings/clock/s5pv210.h>

/* S5PC110/S5PV210 clock controller register offsets */
#define APLL_LOCK		0x0000
#define MPLL_LOCK		0x0008
#define EPLL_LOCK		0x0010
#define VPLL_LOCK		0x0020
#define APLL_CON0		0x0100
#define APLL_CON1		0x0104
#define MPLL_CON		0x0108
#define EPLL_CON0		0x0110
#define EPLL_CON1		0x0114
#define VPLL_CON		0x0120
#define CLK_SRC0		0x0200
#define CLK_SRC1		0x0204
#define CLK_SRC2		0x0208
#define CLK_SRC3		0x020c
#define CLK_SRC4		0x0210
#define CLK_SRC5		0x0214
#define CLK_SRC6		0x0218
#define CLK_SRC_MASK0		0x0280
#define CLK_SRC_MASK1		0x0284
#define CLK_DIV0		0x0300
#define CLK_DIV1		0x0304
#define CLK_DIV2		0x0308
#define CLK_DIV3		0x030c
#define CLK_DIV4		0x0310
#define CLK_DIV5		0x0314
#define CLK_DIV6		0x0318
#define CLK_DIV7		0x031c
#define CLK_GATE_MAIN0		0x0400
#define CLK_GATE_MAIN1		0x0404
#define CLK_GATE_MAIN2		0x0408
#define CLK_GATE_PERI0		0x0420
#define CLK_GATE_PERI1		0x0424
#define CLK_GATE_SCLK0		0x0440
#define CLK_GATE_SCLK1		0x0444
#define CLK_GATE_IP0		0x0460
#define CLK_GATE_IP1		0x0464
#define CLK_GATE_IP2		0x0468
#define CLK_GATE_IP3		0x046c
#define CLK_GATE_IP4		0x0470
#define CLK_GATE_BLOCK		0x0480
#define CLK_GATE_IP5		0x0484
#define CLK_OUT			0x0500
#define MISC			0xe000
#define OM_STAT			0xe100

/* IDs of PLLs available on S5PV210/S5P6442 SoCs */
enum {
	apll,
	mpll,
	epll,
	vpll,
};

/* IDs of external clocks (used for legacy boards) */
enum {
	xxti,
	xusbxti,
};

static void __iomem *reg_base;

/* List of registers that need to be preserved across suspend/resume. */
static unsigned long s5pv210_clk_regs[] __initdata = {
	CLK_SRC0,
	CLK_SRC1,
	CLK_SRC2,
	CLK_SRC3,
	CLK_SRC4,
	CLK_SRC5,
	CLK_SRC6,
	CLK_SRC_MASK0,

Annotation

Implementation Notes