drivers/clk/sophgo/clk-cv1800.c

Source file repositories/reference/linux-study-clean/drivers/clk/sophgo/clk-cv1800.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/sophgo/clk-cv1800.c
Extension
.c
Size
47491 bytes
Lines
1541
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cv1800_clk_desc {
	struct clk_hw_onecell_data	*clks_data;

	int (*pre_init)(struct device *dev, void __iomem *base,
			struct cv1800_clk_ctrl *ctrl,
			const struct cv1800_clk_desc *desc);
};

struct cv1800_clk_ctrl {
	const struct cv1800_clk_desc	*desc;
	spinlock_t			lock;
};

#define CV1800_DIV_FLAG	\
	(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST)
static const struct clk_parent_data osc_parents[] = {
	{ .index = 0 },
};

static const struct cv1800_clk_pll_limit pll_limits[] = {
	{
		.pre_div	= _CV1800_PLL_LIMIT(1, 127),
		.div		= _CV1800_PLL_LIMIT(6, 127),
		.post_div	= _CV1800_PLL_LIMIT(1, 127),
		.ictrl		= _CV1800_PLL_LIMIT(0, 7),
		.mode		= _CV1800_PLL_LIMIT(0, 3),
	},
	{
		.pre_div	= _CV1800_PLL_LIMIT(1, 127),
		.div		= _CV1800_PLL_LIMIT(6, 127),
		.post_div	= _CV1800_PLL_LIMIT(1, 127),
		.ictrl		= _CV1800_PLL_LIMIT(0, 7),
		.mode		= _CV1800_PLL_LIMIT(0, 3),
	},
};

static CV1800_INTEGRAL_PLL(clk_fpll, osc_parents,
			   REG_FPLL_CSR,
			   REG_PLL_G6_CTRL, 8,
			   REG_PLL_G6_STATUS, 2,
			   pll_limits,
			   CLK_IS_CRITICAL);

static CV1800_INTEGRAL_PLL(clk_mipimpll, osc_parents,
			   REG_MIPIMPLL_CSR,
			   REG_PLL_G2_CTRL, 0,
			   REG_PLL_G2_STATUS, 0,
			   pll_limits,
			   CLK_IS_CRITICAL);

static const struct clk_parent_data clk_mipimpll_parents[] = {
	{ .hw = &clk_mipimpll.common.hw },
};
static const struct clk_parent_data clk_bypass_mipimpll_parents[] = {
	{ .index = 0 },
	{ .hw = &clk_mipimpll.common.hw },
};
static const struct clk_parent_data clk_bypass_fpll_parents[] = {
	{ .index = 0 },
	{ .hw = &clk_fpll.common.hw },
};

static struct cv1800_clk_pll_synthesizer clk_mpll_synthesizer = {
	.en		= CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 2),
	.clk_half	= CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 0),
	.ctrl		= REG_MPLL_SSC_SYN_CTRL,
	.set		= REG_MPLL_SSC_SYN_SET,
};
static CV1800_FACTIONAL_PLL(clk_mpll, clk_bypass_mipimpll_parents,
			    REG_MPLL_CSR,
			    REG_PLL_G6_CTRL, 0,
			    REG_PLL_G6_STATUS, 0,
			    pll_limits,
			    &clk_mpll_synthesizer,
			    CLK_IS_CRITICAL);

static struct cv1800_clk_pll_synthesizer clk_tpll_synthesizer = {
	.en		= CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 3),
	.clk_half	= CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 0),
	.ctrl		= REG_TPLL_SSC_SYN_CTRL,
	.set		= REG_TPLL_SSC_SYN_SET,
};
static CV1800_FACTIONAL_PLL(clk_tpll, clk_bypass_mipimpll_parents,
			    REG_TPLL_CSR,
			    REG_PLL_G6_CTRL, 4,
			    REG_PLL_G6_STATUS, 1,
			    pll_limits,
			    &clk_tpll_synthesizer,
			    CLK_IS_CRITICAL);

Annotation

Implementation Notes