drivers/clk/sophgo/clk-cv18xx-ip.c

Source file repositories/reference/linux-study-clean/drivers/clk/sophgo/clk-cv18xx-ip.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/sophgo/clk-cv18xx-ip.c
Extension
.c
Size
21707 bytes
Lines
906
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (tmp_req.rate == req->rate) {
			best_parent = parent;
			best_parent_rate = tmp_req.best_parent_rate;
			best_rate = tmp_req.rate;
			goto find;
		}

		if (div_is_better_rate(common, req->rate,
				       tmp_req.rate, best_rate)) {
			best_parent = parent;
			best_parent_rate = tmp_req.best_parent_rate;
			best_rate = tmp_req.rate;
		}
	}

	if (best_rate == 0)
		return -EINVAL;

find:
	req->best_parent_hw = best_parent;
	req->best_parent_rate = best_parent_rate;
	req->rate = best_rate;
	return 0;
}

static int div_determine_rate(struct clk_hw *hw,
			      struct clk_rate_request *req)
{
	struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);

	return mux_helper_determine_rate(&div->common, req,
					 do_div_determine_rate, div);
}

static unsigned long div_recalc_rate(struct clk_hw *hw,
				     unsigned long parent_rate)
{
	struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
	unsigned long val;

	val = div_helper_get_clockdiv(&div->common, &div->div);
	if (val == 0)
		return 0;

	return divider_recalc_rate(hw, parent_rate, val, NULL,
				   div->div.flags, div->div.width);
}

static int div_set_rate(struct clk_hw *hw, unsigned long rate,
			 unsigned long parent_rate)
{
	struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
	unsigned long val;

	val = divider_get_val(rate, parent_rate, NULL,
			      div->div.width, div->div.flags);

	return div_helper_set_rate(&div->common, &div->div, val);
}

const struct clk_ops cv1800_clk_div_ops = {
	.disable = div_disable,
	.enable = div_enable,
	.is_enabled = div_is_enabled,

	.determine_rate = div_determine_rate,
	.recalc_rate	= div_recalc_rate,
	.set_rate = div_set_rate,
};

static inline struct cv1800_clk_bypass_div *
hw_to_cv1800_clk_bypass_div(struct clk_hw *hw)
{
	struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);

	return container_of(div, struct cv1800_clk_bypass_div, div);
}

static int do_bypass_div_determine_rate(struct clk_rate_request *req, int id,
					void *data)
{
	struct cv1800_clk_bypass_div *div = data;

	if (id == -1) {
		if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) {
			req->rate = req->best_parent_rate;

			return 0;
		}

Annotation

Implementation Notes