drivers/clk/sophgo/clk-cv18xx-ip.h

Source file repositories/reference/linux-study-clean/drivers/clk/sophgo/clk-cv18xx-ip.h

File Facts

System
Linux kernel
Corpus path
drivers/clk/sophgo/clk-cv18xx-ip.h
Extension
.h
Size
8340 bytes
Lines
262
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cv1800_clk_gate {
	struct cv1800_clk_common	common;
	struct cv1800_clk_regbit	gate;
};

struct cv1800_clk_div_data {
	u32		reg;
	u32		mask;
	u32		width;
	u32		init;
	u32		flags;
};

struct cv1800_clk_div {
	struct cv1800_clk_common	common;
	struct cv1800_clk_regbit	gate;
	struct cv1800_clk_regfield	div;
};

struct cv1800_clk_bypass_div {
	struct cv1800_clk_div		div;
	struct cv1800_clk_regbit	bypass;
};

struct cv1800_clk_mux {
	struct cv1800_clk_common	common;
	struct cv1800_clk_regbit	gate;
	struct cv1800_clk_regfield	div;
	struct cv1800_clk_regfield	mux;
};

struct cv1800_clk_bypass_mux {
	struct cv1800_clk_mux		mux;
	struct cv1800_clk_regbit	bypass;
};

struct cv1800_clk_mmux {
	struct cv1800_clk_common	common;
	struct cv1800_clk_regbit	gate;
	struct cv1800_clk_regfield	div[2];
	struct cv1800_clk_regfield	mux[2];
	struct cv1800_clk_regbit	bypass;
	struct cv1800_clk_regbit	clk_sel;
	const s8			*parent2sel;
	const u8			*sel2parent[2];
};

struct cv1800_clk_audio {
	struct cv1800_clk_common	common;
	struct cv1800_clk_regbit	src_en;
	struct cv1800_clk_regbit	output_en;
	struct cv1800_clk_regbit	div_en;
	struct cv1800_clk_regbit	div_up;
	struct cv1800_clk_regfield	m;
	struct cv1800_clk_regfield	n;
	u32				target_rate;
};

#define CV1800_GATE(_name, _parent, _gate_reg, _gate_shift, _flags)	\
	struct cv1800_clk_gate _name = {				\
		.common	= CV1800_CLK_COMMON(#_name, _parent,		\
					    &cv1800_clk_gate_ops,	\
					    _flags),			\
		.gate	= CV1800_CLK_BIT(_gate_reg, _gate_shift),	\
	}

#define _CV1800_DIV(_name, _parent, _gate_reg, _gate_shift,		\
		    _div_reg, _div_shift, _div_width, _div_init,	\
		    _div_flag, _ops, _flags)				\
	{								\
		.common		= CV1800_CLK_COMMON(#_name, _parent,	\
						    _ops, _flags),	\
		.gate		= CV1800_CLK_BIT(_gate_reg,		\
						 _gate_shift),		\
		.div		= CV1800_CLK_REG(_div_reg, _div_shift,	\
						 _div_width, _div_init,	\
						 _div_flag),		\
	}

#define _CV1800_FIXED_DIV_FLAG	\
	(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST)

#define _CV1800_FIXED_DIV(_name, _parent, _gate_reg, _gate_shift,	\
			  _fix_div, _ops, _flags)			\
	{								\
		.common		= CV1800_CLK_COMMON(#_name, _parent,	\
						    _ops, _flags),	\
		.gate		= CV1800_CLK_BIT(_gate_reg,		\
						 _gate_shift),		\
		.div		= CV1800_CLK_REG(0, 0, 0,		\

Annotation

Implementation Notes