drivers/clk/sophgo/clk-sg2042-rpgate.c

Source file repositories/reference/linux-study-clean/drivers/clk/sophgo/clk-sg2042-rpgate.c

File Facts

System: Linux kernel
Corpus path: drivers/clk/sophgo/clk-sg2042-rpgate.c
Extension: .c
Size: 10426 bytes
Lines: 292
Domain: Driver Families
Bucket: drivers/clk
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Allocates kernel memory; connect allocation flags and lifetime to context constraints.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/array_size.h
linux/clk-provider.h
linux/platform_device.h
dt-bindings/clock/sophgo,sg2042-rpgate.h
clk-sg2042.h

Detected Declarations

struct sg2042_rpgate_clock
function sg2042_clk_register_rpgates
function sg2042_init_clkdata
function sg2042_rpgate_probe

Annotated Snippet

struct sg2042_rpgate_clock {
	struct clk_hw hw;

	unsigned int id;

	u32 offset_enable;
	u8 bit_idx;
};

/*
 * Clock initialization macro naming rules:
 * FW: use CLK_HW_INIT_FW_NAME
 */
#define SG2042_GATE_FW(_id, _name, _parent, _flags,	\
		       _r_enable, _bit_idx) {		\
		.hw.init = CLK_HW_INIT_FW_NAME(		\
				_name,			\
				_parent,		\
				NULL,			\
				_flags),		\
		.id = _id,				\
		.offset_enable = _r_enable,		\
		.bit_idx = _bit_idx,			\
	}

/*
 * Gate clocks for RP subsystem (including the MP subsystem), which control
 * registers are defined in SYS_CTRL.
 */
static const struct sg2042_rpgate_clock sg2042_gate_rp[] = {
	/* downstream of clk_gate_rp_cpu_normal about rxu */
	SG2042_GATE_FW(GATE_CLK_RXU0, "clk_gate_rxu0", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 0),
	SG2042_GATE_FW(GATE_CLK_RXU1, "clk_gate_rxu1", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 1),
	SG2042_GATE_FW(GATE_CLK_RXU2, "clk_gate_rxu2", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 2),
	SG2042_GATE_FW(GATE_CLK_RXU3, "clk_gate_rxu3", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 3),
	SG2042_GATE_FW(GATE_CLK_RXU4, "clk_gate_rxu4", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 4),
	SG2042_GATE_FW(GATE_CLK_RXU5, "clk_gate_rxu5", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 5),
	SG2042_GATE_FW(GATE_CLK_RXU6, "clk_gate_rxu6", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 6),
	SG2042_GATE_FW(GATE_CLK_RXU7, "clk_gate_rxu7", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 7),
	SG2042_GATE_FW(GATE_CLK_RXU8, "clk_gate_rxu8", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 8),
	SG2042_GATE_FW(GATE_CLK_RXU9, "clk_gate_rxu9", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 9),
	SG2042_GATE_FW(GATE_CLK_RXU10, "clk_gate_rxu10", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 10),
	SG2042_GATE_FW(GATE_CLK_RXU11, "clk_gate_rxu11", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 11),
	SG2042_GATE_FW(GATE_CLK_RXU12, "clk_gate_rxu12", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 12),
	SG2042_GATE_FW(GATE_CLK_RXU13, "clk_gate_rxu13", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 13),
	SG2042_GATE_FW(GATE_CLK_RXU14, "clk_gate_rxu14", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 14),
	SG2042_GATE_FW(GATE_CLK_RXU15, "clk_gate_rxu15", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 15),
	SG2042_GATE_FW(GATE_CLK_RXU16, "clk_gate_rxu16", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 16),
	SG2042_GATE_FW(GATE_CLK_RXU17, "clk_gate_rxu17", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 17),
	SG2042_GATE_FW(GATE_CLK_RXU18, "clk_gate_rxu18", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 18),
	SG2042_GATE_FW(GATE_CLK_RXU19, "clk_gate_rxu19", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 19),
	SG2042_GATE_FW(GATE_CLK_RXU20, "clk_gate_rxu20", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 20),
	SG2042_GATE_FW(GATE_CLK_RXU21, "clk_gate_rxu21", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 21),
	SG2042_GATE_FW(GATE_CLK_RXU22, "clk_gate_rxu22", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 22),
	SG2042_GATE_FW(GATE_CLK_RXU23, "clk_gate_rxu23", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 23),
	SG2042_GATE_FW(GATE_CLK_RXU24, "clk_gate_rxu24", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 24),
	SG2042_GATE_FW(GATE_CLK_RXU25, "clk_gate_rxu25", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 25),
	SG2042_GATE_FW(GATE_CLK_RXU26, "clk_gate_rxu26", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 26),
	SG2042_GATE_FW(GATE_CLK_RXU27, "clk_gate_rxu27", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 27),
	SG2042_GATE_FW(GATE_CLK_RXU28, "clk_gate_rxu28", "rpgate",
		       0, R_RP_RXU_CLK_ENABLE, 28),
	SG2042_GATE_FW(GATE_CLK_RXU29, "clk_gate_rxu29", "rpgate",

Annotation

Immediate include surface: `linux/array_size.h`, `linux/clk-provider.h`, `linux/platform_device.h`, `dt-bindings/clock/sophgo,sg2042-rpgate.h`, `clk-sg2042.h`.
Detected declarations: `struct sg2042_rpgate_clock`, `function sg2042_clk_register_rpgates`, `function sg2042_init_clkdata`, `function sg2042_rpgate_probe`.
Atlas domain: Driver Families / drivers/clk.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.