drivers/clk/spear/spear1310_clock.c

Source file repositories/reference/linux-study-clean/drivers/clk/spear/spear1310_clock.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/spear/spear1310_clock.c
Extension
.c
Size
43573 bytes
Lines
1120
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * arch/arm/mach-spear13xx/spear1310_clock.c
 *
 * SPEAr1310 machine clock framework source file
 *
 * Copyright (C) 2012 ST Microelectronics
 * Viresh Kumar <vireshk@kernel.org>
 */

#include <linux/clkdev.h>
#include <linux/clk/spear.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spinlock_types.h>
#include "clk.h"

/* PLL related registers and bit values */
#define SPEAR1310_PLL_CFG			(misc_base + 0x210)
	/* PLL_CFG bit values */
	#define SPEAR1310_CLCD_SYNT_CLK_MASK		1
	#define SPEAR1310_CLCD_SYNT_CLK_SHIFT		31
	#define SPEAR1310_RAS_SYNT2_3_CLK_MASK		2
	#define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT		29
	#define SPEAR1310_RAS_SYNT_CLK_MASK		2
	#define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT		27
	#define SPEAR1310_PLL_CLK_MASK			2
	#define SPEAR1310_PLL3_CLK_SHIFT		24
	#define SPEAR1310_PLL2_CLK_SHIFT		22
	#define SPEAR1310_PLL1_CLK_SHIFT		20

#define SPEAR1310_PLL1_CTR			(misc_base + 0x214)
#define SPEAR1310_PLL1_FRQ			(misc_base + 0x218)
#define SPEAR1310_PLL2_CTR			(misc_base + 0x220)
#define SPEAR1310_PLL2_FRQ			(misc_base + 0x224)
#define SPEAR1310_PLL3_CTR			(misc_base + 0x22C)
#define SPEAR1310_PLL3_FRQ			(misc_base + 0x230)
#define SPEAR1310_PLL4_CTR			(misc_base + 0x238)
#define SPEAR1310_PLL4_FRQ			(misc_base + 0x23C)
#define SPEAR1310_PERIP_CLK_CFG			(misc_base + 0x244)
	/* PERIP_CLK_CFG bit values */
	#define SPEAR1310_GPT_OSC24_VAL			0
	#define SPEAR1310_GPT_APB_VAL			1
	#define SPEAR1310_GPT_CLK_MASK			1
	#define SPEAR1310_GPT3_CLK_SHIFT		11
	#define SPEAR1310_GPT2_CLK_SHIFT		10
	#define SPEAR1310_GPT1_CLK_SHIFT		9
	#define SPEAR1310_GPT0_CLK_SHIFT		8
	#define SPEAR1310_UART_CLK_PLL5_VAL		0
	#define SPEAR1310_UART_CLK_OSC24_VAL		1
	#define SPEAR1310_UART_CLK_SYNT_VAL		2
	#define SPEAR1310_UART_CLK_MASK			2
	#define SPEAR1310_UART_CLK_SHIFT		4

	#define SPEAR1310_AUX_CLK_PLL5_VAL		0
	#define SPEAR1310_AUX_CLK_SYNT_VAL		1
	#define SPEAR1310_CLCD_CLK_MASK			2
	#define SPEAR1310_CLCD_CLK_SHIFT		2
	#define SPEAR1310_C3_CLK_MASK			1
	#define SPEAR1310_C3_CLK_SHIFT			1

#define SPEAR1310_GMAC_CLK_CFG			(misc_base + 0x248)
	#define SPEAR1310_GMAC_PHY_IF_SEL_MASK		3
	#define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT		4
	#define SPEAR1310_GMAC_PHY_CLK_MASK		1
	#define SPEAR1310_GMAC_PHY_CLK_SHIFT		3
	#define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK	2
	#define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT	1

#define SPEAR1310_I2S_CLK_CFG			(misc_base + 0x24C)
	/* I2S_CLK_CFG register mask */
	#define SPEAR1310_I2S_SCLK_X_MASK		0x1F
	#define SPEAR1310_I2S_SCLK_X_SHIFT		27
	#define SPEAR1310_I2S_SCLK_Y_MASK		0x1F
	#define SPEAR1310_I2S_SCLK_Y_SHIFT		22
	#define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT		21
	#define SPEAR1310_I2S_SCLK_SYNTH_ENB		20
	#define SPEAR1310_I2S_PRS1_CLK_X_MASK		0xFF
	#define SPEAR1310_I2S_PRS1_CLK_X_SHIFT		12
	#define SPEAR1310_I2S_PRS1_CLK_Y_MASK		0xFF
	#define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT		4
	#define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT		3
	#define SPEAR1310_I2S_REF_SEL_MASK		1
	#define SPEAR1310_I2S_REF_SHIFT			2
	#define SPEAR1310_I2S_SRC_CLK_MASK		2
	#define SPEAR1310_I2S_SRC_CLK_SHIFT		0

#define SPEAR1310_C3_CLK_SYNT			(misc_base + 0x250)
#define SPEAR1310_UART_CLK_SYNT			(misc_base + 0x254)
#define SPEAR1310_GMAC_CLK_SYNT			(misc_base + 0x258)

Annotation

Implementation Notes