drivers/clk/spear/spear3xx_clock.c

Source file repositories/reference/linux-study-clean/drivers/clk/spear/spear3xx_clock.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/spear/spear3xx_clock.c
Extension
.c
Size
23574 bytes
Lines
666
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

static inline void spear300_clk_init(void) { }
#endif

/* array of all spear 310 clock lookups */
#ifdef CONFIG_MACH_SPEAR310
static void __init spear310_clk_init(void)
{
	struct clk *clk;

	clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
			1);
	clk_register_clkdev(clk, "emi", NULL);

	clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
			1);
	clk_register_clkdev(clk, NULL, "44000000.flash");

	clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
			1);
	clk_register_clkdev(clk, NULL, "tdm");

	clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
			1);
	clk_register_clkdev(clk, NULL, "b2000000.serial");

	clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
			1);
	clk_register_clkdev(clk, NULL, "b2080000.serial");

	clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
			1);
	clk_register_clkdev(clk, NULL, "b2100000.serial");

	clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
			1);
	clk_register_clkdev(clk, NULL, "b2180000.serial");

	clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
			1);
	clk_register_clkdev(clk, NULL, "b2200000.serial");
}
#else
static inline void spear310_clk_init(void) { }
#endif

/* array of all spear 320 clock lookups */
#ifdef CONFIG_MACH_SPEAR320

#define SPEAR320_CONTROL_REG		(soc_config_base + 0x0010)
#define SPEAR320_EXT_CTRL_REG		(soc_config_base + 0x0018)

	#define SPEAR320_UARTX_PCLK_MASK		0x1
	#define SPEAR320_UART2_PCLK_SHIFT		8
	#define SPEAR320_UART3_PCLK_SHIFT		9
	#define SPEAR320_UART4_PCLK_SHIFT		10
	#define SPEAR320_UART5_PCLK_SHIFT		11
	#define SPEAR320_UART6_PCLK_SHIFT		12
	#define SPEAR320_RS485_PCLK_SHIFT		13
	#define SMII_PCLK_SHIFT				18
	#define SMII_PCLK_MASK				2
	#define SMII_PCLK_VAL_PAD			0x0
	#define SMII_PCLK_VAL_PLL2			0x1
	#define SMII_PCLK_VAL_SYNTH0			0x2
	#define SDHCI_PCLK_SHIFT			15
	#define SDHCI_PCLK_MASK				1
	#define SDHCI_PCLK_VAL_48M			0x0
	#define SDHCI_PCLK_VAL_SYNTH3			0x1
	#define I2S_REF_PCLK_SHIFT			8
	#define I2S_REF_PCLK_MASK			1
	#define I2S_REF_PCLK_SYNTH_VAL			0x1
	#define I2S_REF_PCLK_PLL2_VAL			0x0
	#define UART1_PCLK_SHIFT			6
	#define UART1_PCLK_MASK				1
	#define SPEAR320_UARTX_PCLK_VAL_SYNTH1		0x0
	#define SPEAR320_UARTX_PCLK_VAL_APB		0x1

static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", };
static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", };
static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
	"ras_syn0_gclk", };
static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };

static void __init spear320_clk_init(void __iomem *soc_config_base,
				     struct clk *ras_apb_clk)
{
	struct clk *clk;

	clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
			0, 125000000);
	clk_register_clkdev(clk, "smii_125m_pad", NULL);

Annotation

Implementation Notes