drivers/clk/sprd/pll.h
Source file repositories/reference/linux-study-clean/drivers/clk/sprd/pll.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/sprd/pll.h- Extension
.h- Size
- 3275 bytes
- Lines
- 128
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
common.h
Detected Declarations
struct reg_cfgstruct clk_bit_fieldstruct sprd_pll
Annotated Snippet
struct reg_cfg {
u32 val;
u32 msk;
};
struct clk_bit_field {
u8 shift;
u8 width;
};
enum {
PLL_LOCK_DONE,
PLL_DIV_S,
PLL_MOD_EN,
PLL_SDM_EN,
PLL_REFIN,
PLL_IBIAS,
PLL_N,
PLL_NINT,
PLL_KINT,
PLL_PREDIV,
PLL_POSTDIV,
PLL_FACT_MAX
};
/*
* struct sprd_pll - definition of adjustable pll clock
*
* @reg: registers used to set the configuration of pll clock,
* reg[0] shows how many registers this pll clock uses.
* @itable: pll ibias table, itable[0] means how many items this
* table includes
* @udelay delay time after setting rate
* @factors used to calculate the pll clock rate
* @fvco: fvco threshold rate
* @fflag: fvco flag
*/
struct sprd_pll {
u32 regs_num;
const u64 *itable;
const struct clk_bit_field *factors;
u16 udelay;
u16 k1;
u16 k2;
u16 fflag;
u64 fvco;
struct sprd_clk_common common;
};
#define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \
_regs_num, _itable, _factors, \
_udelay, _k1, _k2, _fflag, \
_fvco, _fn) \
struct sprd_pll _struct = { \
.regs_num = _regs_num, \
.itable = _itable, \
.factors = _factors, \
.udelay = _udelay, \
.k1 = _k1, \
.k2 = _k2, \
.fflag = _fflag, \
.fvco = _fvco, \
.common = { \
.regmap = NULL, \
.reg = _reg, \
.hw.init = _fn(_name, _parent, \
&sprd_pll_ops, 0),\
}, \
}
#define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
_regs_num, _itable, _factors, \
_udelay, _k1, _k2, _fflag, _fvco) \
SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
_itable, _factors, _udelay, _k1, _k2, \
_fflag, _fvco, CLK_HW_INIT)
#define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \
_regs_num, _itable, _factors, \
_udelay, _k1, _k2) \
SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
_regs_num, _itable, _factors, \
_udelay, _k1, _k2, 0, 0)
#define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \
_regs_num, _itable, _factors, _udelay) \
SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
_regs_num, _itable, _factors, \
Annotation
- Immediate include surface: `common.h`.
- Detected declarations: `struct reg_cfg`, `struct clk_bit_field`, `struct sprd_pll`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.