drivers/clk/st/clkgen-fsyn.c
Source file repositories/reference/linux-study-clean/drivers/clk/st/clkgen-fsyn.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/st/clkgen-fsyn.c- Extension
.c- Size
- 27371 bytes
- Lines
- 1072
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/slab.hlinux/of_address.hlinux/clk.hlinux/clk-provider.hclkgen.h
Detected Declarations
struct stm_fsstruct clkgen_quadfs_datastruct clkgen_clk_outstruct clkgen_quadfs_data_clksstruct st_clk_quadfs_pllstruct st_clk_quadfs_fsynthfunction quadfs_pll_enablefunction quadfs_pll_disablefunction quadfs_pll_is_enabledfunction clk_fs660c32_vco_get_ratefunction quadfs_pll_fs660c32_recalc_ratefunction clk_fs660c32_vco_get_paramsfunction quadfs_pll_fs660c32_determine_ratefunction quadfs_pll_fs660c32_set_ratefunction st_clk_register_quadfs_pllfunction quadfs_fsynth_program_enablefunction quadfs_fsynth_program_ratefunction quadfs_fsynth_enablefunction quadfs_fsynth_disablefunction quadfs_fsynth_is_enabledfunction clk_fs660c32_dig_get_ratefunction clk_fs660c32_get_pefunction clk_fs660c32_dig_get_paramsfunction quadfs_fsynt_get_hw_value_for_recalcfunction quadfs_find_best_ratefunction quadfs_recalc_ratefunction quadfs_determine_ratefunction quadfs_program_and_enablefunction quadfs_set_ratefunction st_clk_register_quadfs_fsynthfunction st_of_create_quadfs_fsynthsfunction st_of_quadfs_setupfunction st_of_quadfs660C_setupfunction st_of_quadfs660D_setupfunction st_of_quadfs660D0_setupfunction st_of_quadfs660D2_setupfunction st_of_quadfs660D3_setup
Annotated Snippet
struct stm_fs {
unsigned long ndiv;
unsigned long mdiv;
unsigned long pe;
unsigned long sdiv;
unsigned long nsdiv;
};
struct clkgen_quadfs_data {
bool reset_present;
bool bwfilter_present;
bool lockstatus_present;
bool powerup_polarity;
bool standby_polarity;
bool nsdiv_present;
bool nrst_present;
struct clkgen_field ndiv;
struct clkgen_field ref_bw;
struct clkgen_field nreset;
struct clkgen_field npda;
struct clkgen_field lock_status;
struct clkgen_field nrst[QUADFS_MAX_CHAN];
struct clkgen_field nsb[QUADFS_MAX_CHAN];
struct clkgen_field en[QUADFS_MAX_CHAN];
struct clkgen_field mdiv[QUADFS_MAX_CHAN];
struct clkgen_field pe[QUADFS_MAX_CHAN];
struct clkgen_field sdiv[QUADFS_MAX_CHAN];
struct clkgen_field nsdiv[QUADFS_MAX_CHAN];
const struct clk_ops *pll_ops;
int (*get_params)(unsigned long, unsigned long, struct stm_fs *);
int (*get_rate)(unsigned long , const struct stm_fs *,
unsigned long *);
};
struct clkgen_clk_out {
const char *name;
unsigned long flags;
};
struct clkgen_quadfs_data_clks {
struct clkgen_quadfs_data *data;
const struct clkgen_clk_out *outputs;
};
static const struct clk_ops st_quadfs_pll_c32_ops;
static int clk_fs660c32_dig_get_params(unsigned long input,
unsigned long output, struct stm_fs *fs);
static int clk_fs660c32_dig_get_rate(unsigned long, const struct stm_fs *,
unsigned long *);
static const struct clkgen_quadfs_data st_fs660c32_C = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
CLKGEN_FIELD(0x2f0, 0x1, 1),
CLKGEN_FIELD(0x2f0, 0x1, 2),
CLKGEN_FIELD(0x2f0, 0x1, 3) },
.npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
.nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
CLKGEN_FIELD(0x2f0, 0x1, 9),
CLKGEN_FIELD(0x2f0, 0x1, 10),
CLKGEN_FIELD(0x2f0, 0x1, 11) },
.nsdiv_present = true,
.nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
CLKGEN_FIELD(0x308, 0x1, 24),
CLKGEN_FIELD(0x30c, 0x1, 24),
CLKGEN_FIELD(0x310, 0x1, 24) },
.mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
CLKGEN_FIELD(0x308, 0x1f, 15),
CLKGEN_FIELD(0x30c, 0x1f, 15),
CLKGEN_FIELD(0x310, 0x1f, 15) },
.en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
CLKGEN_FIELD(0x2fc, 0x1, 1),
CLKGEN_FIELD(0x2fc, 0x1, 2),
CLKGEN_FIELD(0x2fc, 0x1, 3) },
.ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
.pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
CLKGEN_FIELD(0x308, 0x7fff, 0),
CLKGEN_FIELD(0x30c, 0x7fff, 0),
CLKGEN_FIELD(0x310, 0x7fff, 0) },
.sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
CLKGEN_FIELD(0x308, 0xf, 20),
CLKGEN_FIELD(0x30c, 0xf, 20),
CLKGEN_FIELD(0x310, 0xf, 20) },
.lockstatus_present = true,
.lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24),
.powerup_polarity = 1,
.standby_polarity = 1,
Annotation
- Immediate include surface: `linux/slab.h`, `linux/of_address.h`, `linux/clk.h`, `linux/clk-provider.h`, `clkgen.h`.
- Detected declarations: `struct stm_fs`, `struct clkgen_quadfs_data`, `struct clkgen_clk_out`, `struct clkgen_quadfs_data_clks`, `struct st_clk_quadfs_pll`, `struct st_clk_quadfs_fsynth`, `function quadfs_pll_enable`, `function quadfs_pll_disable`, `function quadfs_pll_is_enabled`, `function clk_fs660c32_vco_get_rate`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.