drivers/clk/starfive/clk-starfive-jh7100-audio.c

Source file repositories/reference/linux-study-clean/drivers/clk/starfive/clk-starfive-jh7100-audio.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/starfive/clk-starfive-jh7100-audio.c
Extension
.c
Size
6136 bytes
Lines
160
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * StarFive JH7100 Audio Clock Driver
 *
 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
 */

#include <linux/bits.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>

#include <dt-bindings/clock/starfive-jh7100-audio.h>

#include "clk-starfive-jh71x0.h"

/* external clocks */
#define JH7100_AUDCLK_AUDIO_SRC			(JH7100_AUDCLK_END + 0)
#define JH7100_AUDCLK_AUDIO_12288		(JH7100_AUDCLK_END + 1)
#define JH7100_AUDCLK_DOM7AHB_BUS		(JH7100_AUDCLK_END + 2)
#define JH7100_AUDCLK_I2SADC_BCLK_IOPAD		(JH7100_AUDCLK_END + 3)
#define JH7100_AUDCLK_I2SADC_LRCLK_IOPAD	(JH7100_AUDCLK_END + 4)
#define JH7100_AUDCLK_I2SDAC_BCLK_IOPAD		(JH7100_AUDCLK_END + 5)
#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD	(JH7100_AUDCLK_END + 6)
#define JH7100_AUDCLK_VAD_INTMEM                (JH7100_AUDCLK_END + 7)

static const struct jh71x0_clk_data jh7100_audclk_data[] = {
	JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
		    JH7100_AUDCLK_AUDIO_SRC,
		    JH7100_AUDCLK_AUDIO_12288),
	JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
		    JH7100_AUDCLK_AUDIO_SRC,
		    JH7100_AUDCLK_AUDIO_12288),
	JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
	JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
		    JH7100_AUDCLK_ADC_MCLK,
		    JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
	JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
	JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
		    JH7100_AUDCLK_I2SADC_BCLK_N,
		    JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
		    JH7100_AUDCLK_I2SADC_BCLK),
	JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
	JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
		    JH7100_AUDCLK_AUDIO_SRC,
		    JH7100_AUDCLK_AUDIO_12288),
	JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
	JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
		    JH7100_AUDCLK_AUDIO_SRC,
		    JH7100_AUDCLK_AUDIO_12288),
	JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
	JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
	JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
		    JH7100_AUDCLK_AUDIO_SRC,
		    JH7100_AUDCLK_AUDIO_12288),
	JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
	JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
		    JH7100_AUDCLK_DAC_MCLK,
		    JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
	JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
	JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
		    JH7100_AUDCLK_I2S1_MCLK,
		    JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
	JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
	JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
		    JH7100_AUDCLK_I2S1_MCLK,
		    JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
	JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
	JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
		    JH7100_AUDCLK_I2S1_BCLK_N,
		    JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
	JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
	JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
	JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
	JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
	JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
	JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
	JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
	JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 0, 2,
		    JH7100_AUDCLK_VAD_INTMEM,
		    JH7100_AUDCLK_AUDIO_12288),
};

static int jh7100_audclk_probe(struct platform_device *pdev)
{
	struct jh71x0_clk_priv *priv;
	unsigned int idx;

Annotation

Implementation Notes