drivers/clk/starfive/clk-starfive-jh7100.c

Source file repositories/reference/linux-study-clean/drivers/clk/starfive/clk-starfive-jh7100.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/starfive/clk-starfive-jh7100.c
Extension
.c
Size
19335 bytes
Lines
370
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * StarFive JH7100 Clock Generator Driver
 *
 * Copyright 2021 Ahmad Fatoum, Pengutronix
 * Copyright (C) 2021 Glider bv
 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
 */

#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>

#include <dt-bindings/clock/starfive-jh7100.h>

#include "clk-starfive-jh71x0.h"

/* external clocks */
#define JH7100_CLK_OSC_SYS		(JH7100_CLK_END + 0)
#define JH7100_CLK_OSC_AUD		(JH7100_CLK_END + 1)
#define JH7100_CLK_GMAC_RMII_REF	(JH7100_CLK_END + 2)
#define JH7100_CLK_GMAC_GR_MII_RX	(JH7100_CLK_END + 3)

static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
	JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 0, 4,
		    JH7100_CLK_OSC_SYS,
		    JH7100_CLK_PLL0_OUT,
		    JH7100_CLK_PLL1_OUT,
		    JH7100_CLK_PLL2_OUT),
	JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 0, 3,
		    JH7100_CLK_OSC_SYS,
		    JH7100_CLK_PLL1_OUT,
		    JH7100_CLK_PLL2_OUT),
	JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 0, 4,
		    JH7100_CLK_OSC_SYS,
		    JH7100_CLK_PLL0_OUT,
		    JH7100_CLK_PLL1_OUT,
		    JH7100_CLK_PLL2_OUT),
	JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 0, 3,
		    JH7100_CLK_OSC_SYS,
		    JH7100_CLK_PLL0_OUT,
		    JH7100_CLK_PLL2_OUT),
	JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 0, 2,
		    JH7100_CLK_OSC_SYS,
		    JH7100_CLK_PLL0_OUT),
	JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 0, 2,
		    JH7100_CLK_OSC_SYS,
		    JH7100_CLK_PLL2_OUT),
	JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 0, 3,
		    JH7100_CLK_OSC_SYS,
		    JH7100_CLK_PLL1_OUT,
		    JH7100_CLK_PLL2_OUT),
	JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 0, 3,
		    JH7100_CLK_OSC_AUD,
		    JH7100_CLK_PLL0_OUT,
		    JH7100_CLK_PLL2_OUT),
	JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
	JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 0, 3,
		    JH7100_CLK_OSC_SYS,
		    JH7100_CLK_PLL1_OUT,
		    JH7100_CLK_PLL2_OUT),
	JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 0, 3,
		    JH7100_CLK_OSC_SYS,
		    JH7100_CLK_PLL0_OUT,
		    JH7100_CLK_PLL1_OUT),
	JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 0, 3,
		    JH7100_CLK_OSC_AUD,
		    JH7100_CLK_PLL0_OUT,
		    JH7100_CLK_PLL2_OUT),
	JH71X0__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
	JH71X0__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
	JH71X0__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
	JH71X0__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
	JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
	JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
	JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
	JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 0, 2,
		    JH7100_CLK_OSC_SYS,
		    JH7100_CLK_OSC_AUD),
	JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
	JH71X0__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
	JH71X0__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
	JH71X0__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
	JH71X0__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
	JH71X0_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
	JH71X0_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
	JH71X0_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
	JH71X0_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),

Annotation

Implementation Notes