drivers/clk/starfive/clk-starfive-jh7110-vout.c
Source file repositories/reference/linux-study-clean/drivers/clk/starfive/clk-starfive-jh7110-vout.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/starfive/clk-starfive-jh7110-vout.c- Extension
.c- Size
- 7088 bytes
- Lines
- 228
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/clk-provider.hlinux/io.hlinux/platform_device.hlinux/pm_runtime.hlinux/reset.hdt-bindings/clock/starfive,jh7110-crg.hclk-starfive-jh7110.h
Detected Declarations
function jh7110_vout_top_rst_initfunction jh7110_voutcrg_suspendfunction jh7110_voutcrg_resumefunction jh7110_voutcrg_probefunction jh7110_voutcrg_remove
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* StarFive JH7110 Video-Output Clock Driver
*
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include "clk-starfive-jh7110.h"
/* external clocks */
#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0)
#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1)
#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2)
#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3)
#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4)
#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5)
#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6)
static struct clk_bulk_data jh7110_vout_top_clks[] = {
{ .id = "vout_src" },
{ .id = "vout_top_ahb" }
};
static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
/* divider */
JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
/* dc8200 */
JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
JH7110_VOUTCLK_DC8200_PIX,
JH7110_VOUTCLK_HDMITX0_PIXELCLK),
JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
JH7110_VOUTCLK_DC8200_PIX,
JH7110_VOUTCLK_HDMITX0_PIXELCLK),
/* LCD */
JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
JH7110_VOUTCLK_DC8200_PIX0,
JH7110_VOUTCLK_DC8200_PIX1),
/* dsiTx */
JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
JH7110_VOUTCLK_DC8200_PIX,
JH7110_VOUTCLK_HDMITX0_PIXELCLK),
JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
/* mipitx DPHY */
JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
JH7110_VOUTCLK_TX_ESC),
/* hdmi */
JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
JH7110_VOUTCLK_I2STX0_BCLK),
JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
};
static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv)
{
struct reset_control *top_rst;
/* The reset should be shared and other Vout modules will use its. */
top_rst = devm_reset_control_get_shared(priv->dev, NULL);
if (IS_ERR(top_rst))
return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n");
return reset_control_deassert(top_rst);
}
#ifdef CONFIG_PM
static int jh7110_voutcrg_suspend(struct device *dev)
{
struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
return 0;
Annotation
- Immediate include surface: `linux/clk.h`, `linux/clk-provider.h`, `linux/io.h`, `linux/platform_device.h`, `linux/pm_runtime.h`, `linux/reset.h`, `dt-bindings/clock/starfive,jh7110-crg.h`, `clk-starfive-jh7110.h`.
- Detected declarations: `function jh7110_vout_top_rst_init`, `function jh7110_voutcrg_suspend`, `function jh7110_voutcrg_resume`, `function jh7110_voutcrg_probe`, `function jh7110_voutcrg_remove`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.