drivers/clk/starfive/clk-starfive-jh71x0.c
Source file repositories/reference/linux-study-clean/drivers/clk/starfive/clk-starfive-jh71x0.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/starfive/clk-starfive-jh71x0.c- Extension
.c- Size
- 9656 bytes
- Lines
- 340
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk-provider.hlinux/debugfs.hlinux/device.hlinux/io.hclk-starfive-jh71x0.h
Detected Declarations
function Copyrightfunction jh71x0_clk_reg_getfunction jh71x0_clk_reg_rmwfunction jh71x0_clk_enablefunction jh71x0_clk_disablefunction jh71x0_clk_is_enabledfunction jh71x0_clk_recalc_ratefunction jh71x0_clk_determine_ratefunction jh71x0_clk_set_ratefunction jh71x0_clk_frac_recalc_ratefunction jh71x0_clk_frac_determine_ratefunction jh71x0_clk_frac_set_ratefunction jh71x0_clk_get_parentfunction jh71x0_clk_set_parentfunction jh71x0_clk_get_phasefunction jh71x0_clk_set_phasefunction jh71x0_clk_debug_initexport starfive_jh71x0_clk_opsexport jh71x0_clk_get
Annotated Snippet
if (max & JH71X0_CLK_MUX_MASK) {
if (max & JH71X0_CLK_ENABLE)
return &jh71x0_clk_gmd_ops;
return &jh71x0_clk_mdiv_ops;
}
if (max & JH71X0_CLK_ENABLE)
return &jh71x0_clk_gdiv_ops;
if (max == JH71X0_CLK_FRAC_MAX)
return &jh71x0_clk_fdiv_ops;
return &jh71x0_clk_div_ops;
}
if (max & JH71X0_CLK_MUX_MASK) {
if (max & JH71X0_CLK_ENABLE)
return &jh71x0_clk_gmux_ops;
return &jh71x0_clk_mux_ops;
}
if (max & JH71X0_CLK_ENABLE)
return &jh71x0_clk_gate_ops;
return &jh71x0_clk_inv_ops;
}
EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);
struct clk_hw *jh71x0_clk_get(struct of_phandle_args *clkspec, void *data)
{
struct jh71x0_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < priv->num_reg)
return &priv->reg[idx].hw;
return ERR_PTR(-EINVAL);
}
EXPORT_SYMBOL_GPL(jh71x0_clk_get);
Annotation
- Immediate include surface: `linux/clk-provider.h`, `linux/debugfs.h`, `linux/device.h`, `linux/io.h`, `clk-starfive-jh71x0.h`.
- Detected declarations: `function Copyright`, `function jh71x0_clk_reg_get`, `function jh71x0_clk_reg_rmw`, `function jh71x0_clk_enable`, `function jh71x0_clk_disable`, `function jh71x0_clk_is_enabled`, `function jh71x0_clk_recalc_rate`, `function jh71x0_clk_determine_rate`, `function jh71x0_clk_set_rate`, `function jh71x0_clk_frac_recalc_rate`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.