drivers/clk/starfive/clk-starfive-jh71x0.h

Source file repositories/reference/linux-study-clean/drivers/clk/starfive/clk-starfive-jh71x0.h

File Facts

System
Linux kernel
Corpus path
drivers/clk/starfive/clk-starfive-jh71x0.h
Extension
.h
Size
3327 bytes
Lines
128
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct jh71x0_clk_data {
	const char *name;
	unsigned long flags;
	u32 max;
	u8 parents[4];
};

#define JH71X0_GATE(_idx, _name, _flags, _parent)				\
[_idx] = {									\
	.name = _name,								\
	.flags = CLK_SET_RATE_PARENT | (_flags),				\
	.max = JH71X0_CLK_ENABLE,						\
	.parents = { [0] = _parent },						\
}

#define JH71X0__DIV(_idx, _name, _max, _parent)					\
[_idx] = {									\
	.name = _name,								\
	.flags = 0,								\
	.max = _max,								\
	.parents = { [0] = _parent },						\
}

#define JH71X0_GDIV(_idx, _name, _flags, _max, _parent)				\
[_idx] = {									\
	.name = _name,								\
	.flags = _flags,							\
	.max = JH71X0_CLK_ENABLE | (_max),					\
	.parents = { [0] = _parent },						\
}

#define JH71X0_FDIV(_idx, _name, _parent)					\
[_idx] = {									\
	.name = _name,								\
	.flags = 0,								\
	.max = JH71X0_CLK_FRAC_MAX,						\
	.parents = { [0] = _parent },						\
}

#define JH71X0__MUX(_idx, _name, _flags, _nparents, ...)			\
[_idx] = {									\
	.name = _name,								\
	.flags = _flags,							\
	.max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT,			\
	.parents = { __VA_ARGS__ },						\
}

#define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...)			\
[_idx] = {									\
	.name = _name,								\
	.flags = _flags,							\
	.max = JH71X0_CLK_ENABLE |						\
		(((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT),			\
	.parents = { __VA_ARGS__ },						\
}

#define JH71X0_MDIV(_idx, _name, _max, _nparents, ...)				\
[_idx] = {									\
	.name = _name,								\
	.flags = 0,								\
	.max = (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max),		\
	.parents = { __VA_ARGS__ },						\
}

#define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...)			\
[_idx] = {									\
	.name = _name,								\
	.flags = _flags,							\
	.max = JH71X0_CLK_ENABLE |						\
		(((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max),		\
	.parents = { __VA_ARGS__ },						\
}

#define JH71X0__INV(_idx, _name, _parent)					\
[_idx] = {									\
	.name = _name,								\
	.flags = CLK_SET_RATE_PARENT,						\
	.max = JH71X0_CLK_INVERT,						\
	.parents = { [0] = _parent },						\
}

struct jh71x0_clk {
	struct clk_hw hw;
	unsigned int idx;
	unsigned int max_div;
};

struct jh71x0_clk_priv {
	/* protect clk enable and set rate/parent from happening at the same time */
	spinlock_t rmw_lock;

Annotation

Implementation Notes