drivers/clk/sunxi/clk-sun9i-cpus.c

Source file repositories/reference/linux-study-clean/drivers/clk/sunxi/clk-sun9i-cpus.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/sunxi/clk-sun9i-cpus.c
Extension
.c
Size
6370 bytes
Lines
244
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct sun9i_a80_cpus_clk {
	struct clk_hw hw;
	void __iomem *reg;
};

#define to_sun9i_a80_cpus_clk(_hw) container_of(_hw, struct sun9i_a80_cpus_clk, hw)

static unsigned long sun9i_a80_cpus_clk_recalc_rate(struct clk_hw *hw,
						    unsigned long parent_rate)
{
	struct sun9i_a80_cpus_clk *cpus = to_sun9i_a80_cpus_clk(hw);
	unsigned long rate;
	u32 reg;

	/* Fetch the register value */
	reg = readl(cpus->reg);

	/* apply pre-divider first if parent is pll4 */
	if (SUN9I_CPUS_MUX_GET_PARENT(reg) == SUN9I_CPUS_MUX_PARENT_PLL4)
		parent_rate /= SUN9I_CPUS_PLL4_DIV_GET(reg) + 1;

	/* clk divider */
	rate = parent_rate / (SUN9I_CPUS_DIV_GET(reg) + 1);

	return rate;
}

static long sun9i_a80_cpus_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
				     u8 parent, unsigned long parent_rate)
{
	u8 div, pre_div = 1;

	/*
	 * clock can only divide, so we will never be able to achieve
	 * frequencies higher than the parent frequency
	 */
	if (parent_rate && rate > parent_rate)
		rate = parent_rate;

	div = DIV_ROUND_UP(parent_rate, rate);

	/* calculate pre-divider if parent is pll4 */
	if (parent == SUN9I_CPUS_MUX_PARENT_PLL4 && div > 4) {
		/* pre-divider is 1 ~ 32 */
		if (div < 32) {
			pre_div = div;
			div = 1;
		} else if (div < 64) {
			pre_div = DIV_ROUND_UP(div, 2);
			div = 2;
		} else if (div < 96) {
			pre_div = DIV_ROUND_UP(div, 3);
			div = 3;
		} else {
			pre_div = DIV_ROUND_UP(div, 4);
			div = 4;
		}
	}

	/* we were asked to pass back divider values */
	if (divp) {
		*divp = div - 1;
		*pre_divp = pre_div - 1;
	}

	return parent_rate / pre_div / div;
}

static int sun9i_a80_cpus_clk_determine_rate(struct clk_hw *clk,
					     struct clk_rate_request *req)
{
	struct clk_hw *parent, *best_parent = NULL;
	int i, num_parents;
	unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
	unsigned long rate = req->rate;

	/* find the parent that can help provide the fastest rate <= rate */
	num_parents = clk_hw_get_num_parents(clk);
	for (i = 0; i < num_parents; i++) {
		parent = clk_hw_get_parent_by_index(clk, i);
		if (!parent)
			continue;
		if (clk_hw_get_flags(clk) & CLK_SET_RATE_PARENT)
			parent_rate = clk_hw_round_rate(parent, rate);
		else
			parent_rate = clk_hw_get_rate(parent);

		child_rate = sun9i_a80_cpus_clk_round(rate, NULL, NULL, i,
						      parent_rate);

Annotation

Implementation Notes