drivers/clk/sunxi-ng/ccu_nm.h

Source file repositories/reference/linux-study-clean/drivers/clk/sunxi-ng/ccu_nm.h

File Facts

System
Linux kernel
Corpus path
drivers/clk/sunxi-ng/ccu_nm.h
Extension
.h
Size
5656 bytes
Lines
210
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ccu_nm {
	u32			enable;
	u32			lock;

	struct ccu_mult_internal	n;
	struct ccu_div_internal		m;
	struct ccu_frac_internal	frac;
	struct ccu_sdm_internal		sdm;

	unsigned int		fixed_post_div;
	unsigned int		min_rate;
	unsigned int		max_rate;

	struct ccu_common	common;
};

#define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg,	\
					_nshift, _nwidth,		\
					_mshift, _mwidth,		\
					_sdm_table, _sdm_en,		\
					_sdm_reg, _sdm_reg_en,		\
					_gate, _lock, _flags)		\
	struct ccu_nm _struct = {					\
		.enable		= _gate,				\
		.lock		= _lock,				\
		.n		= _SUNXI_CCU_MULT(_nshift, _nwidth),	\
		.m		= _SUNXI_CCU_DIV(_mshift, _mwidth),	\
		.sdm		= _SUNXI_CCU_SDM(_sdm_table, _sdm_en,	\
						 _sdm_reg, _sdm_reg_en),\
		.common		= {					\
			.reg		= _reg,				\
			.features	= CCU_FEATURE_SIGMA_DELTA_MOD,	\
			.hw.init	= CLK_HW_INIT(_name,		\
						      _parent,		\
						      &ccu_nm_ops,	\
						      _flags),		\
		},							\
	}

#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg,	\
					 _nshift, _nwidth,		\
					 _mshift, _mwidth,		\
					 _frac_en, _frac_sel,		\
					 _frac_rate_0, _frac_rate_1,	\
					 _gate, _lock, _flags)		\
	struct ccu_nm _struct = {					\
		.enable		= _gate,				\
		.lock		= _lock,				\
		.n		= _SUNXI_CCU_MULT(_nshift, _nwidth),	\
		.m		= _SUNXI_CCU_DIV(_mshift, _mwidth),	\
		.frac		= _SUNXI_CCU_FRAC(_frac_en, _frac_sel,	\
						  _frac_rate_0,		\
						  _frac_rate_1),	\
		.common		= {					\
			.reg		= _reg,				\
			.features	= CCU_FEATURE_FRACTIONAL,	\
			.hw.init	= CLK_HW_INIT(_name,		\
						      _parent,		\
						      &ccu_nm_ops,	\
						      _flags),		\
		},							\
	}

#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent,	\
					     _reg, _min_rate,		\
					     _nshift, _nwidth,		\
					     _mshift, _mwidth,		\
					     _frac_en, _frac_sel,	\
					     _frac_rate_0, _frac_rate_1,\
					     _gate, _lock, _flags)	\
	struct ccu_nm _struct = {					\
		.enable		= _gate,				\
		.lock		= _lock,				\
		.n		= _SUNXI_CCU_MULT(_nshift, _nwidth),	\
		.m		= _SUNXI_CCU_DIV(_mshift, _mwidth),	\
		.frac		= _SUNXI_CCU_FRAC(_frac_en, _frac_sel,	\
						  _frac_rate_0,		\
						  _frac_rate_1),	\
		.min_rate	= _min_rate,				\
		.common		= {					\
			.reg		= _reg,				\
			.features	= CCU_FEATURE_FRACTIONAL,	\
			.hw.init	= CLK_HW_INIT(_name,		\
						      _parent,		\
						      &ccu_nm_ops,	\
						      _flags),		\
		},							\
	}

#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT(_struct, _name,	\

Annotation

Implementation Notes