drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c

Source file repositories/reference/linux-study-clean/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
Extension
.c
Size
8445 bytes
Lines
265
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2024 Arm Ltd.
 * Based on the D1 CCU driver:
 *   Copyright (c) 2020 huangzhenwei@allwinnertech.com
 *   Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>

#include "ccu_common.h"
#include "ccu_reset.h"

#include "ccu_gate.h"
#include "ccu_mp.h"

#include "ccu-sun55i-a523-r.h"

static const struct clk_parent_data r_ahb_apb_parents[] = {
	{ .fw_name = "hosc" },
	{ .fw_name = "losc" },
	{ .fw_name = "iosc" },
	{ .fw_name = "pll-periph" },
	{ .fw_name = "pll-audio" },
};
static SUNXI_CCU_M_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
				 r_ahb_apb_parents, 0x000,
				 0, 5,	/* M */
				 24, 3,	/* mux */
				 0);

static SUNXI_CCU_M_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
				 r_ahb_apb_parents, 0x00c,
				 0, 5,	/* M */
				 24, 3,	/* mux */
				 0);

static SUNXI_CCU_M_DATA_WITH_MUX(r_apb1_clk, "r-apb1",
				 r_ahb_apb_parents, 0x010,
				 0, 5,	/* M */
				 24, 3,	/* mux */
				 0);

static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0",
				       r_ahb_apb_parents, 0x100,
				       0, 0,	/* no M */
				       1, 3,	/* P */
				       4, 3,	/* mux */
				       BIT(0),
				      0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1",
				       r_ahb_apb_parents, 0x104,
				       0, 0,	/* no M */
				       1, 3,	/* P */
				       4, 3,	/* mux */
				       BIT(0),
				       0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2",
				       r_ahb_apb_parents, 0x108,
				       0, 0,	/* no M */
				       1, 3,	/* P */
				       4, 3,	/* mux */
				       BIT(0),
				       0);

static SUNXI_CCU_GATE_HW(bus_r_timer_clk, "bus-r-timer", &r_ahb_clk.common.hw,
			 0x11c, BIT(0), 0);
static SUNXI_CCU_GATE_HW(bus_r_twd_clk,	"bus-r-twd", &r_apb0_clk.common.hw,
			 0x12c, BIT(0), 0);

static const struct clk_parent_data r_pwmctrl_parents[] = {
	{ .fw_name = "hosc" },
	{ .fw_name = "losc" },
	{ .fw_name = "iosc" },
};
static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl",
				  r_pwmctrl_parents, 0x130,
				  24, 2,	/* mux */
				  BIT(31),
				  0);
static SUNXI_CCU_GATE_HW(bus_r_pwmctrl_clk, "bus-r-pwmctrl",
			 &r_apb0_clk.common.hw, 0x13c, BIT(0), 0);

static const struct clk_parent_data r_spi_parents[] = {
	{ .fw_name = "hosc" },
	{ .fw_name = "pll-periph" },
	{ .name = "pll-periph0-300M" },
	{ .name = "pll-periph1-300M" },

Annotation

Implementation Notes