drivers/clk/tegra/clk-tegra-super-gen4.c

Source file repositories/reference/linux-study-clean/drivers/clk/tegra/clk-tegra-super-gen4.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/tegra/clk-tegra-super-gen4.c
Extension
.c
Size
7655 bytes
Lines
270
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct tegra_super_gen_info {
	enum tegra_super_gen gen;
	const char **sclk_parents;
	const char **cclk_g_parents;
	const char **cclk_lp_parents;
	int num_sclk_parents;
	int num_cclk_g_parents;
	int num_cclk_lp_parents;
};

static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
			       "pll_p", "pll_p_out2", "unused",
			       "clk_32k", "pll_m_out1" };

static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
					"pll_p", "pll_p_out4", "unused",
					"unused", "pll_x", "unused", "unused",
					"unused", "unused", "unused", "unused",
					"dfllCPU_out" };

static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
					 "pll_p", "pll_p_out4", "unused",
					 "unused", "pll_x", "pll_x_out0" };

static const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {
	.gen = gen4,
	.sclk_parents = sclk_parents,
	.cclk_g_parents = cclk_g_parents,
	.cclk_lp_parents = cclk_lp_parents,
	.num_sclk_parents = ARRAY_SIZE(sclk_parents),
	.num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents),
	.num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents),
};

static const char *sclk_parents_gen5[] = { "clk_m", "pll_c_out1", "pll_c4_out3",
			       "pll_p", "pll_p_out2", "pll_c4_out1",
			       "clk_32k", "pll_c4_out2" };

static const char *cclk_g_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
					"pll_p", "pll_p_out4", "unused",
					"unused", "pll_x", "unused", "unused",
					"unused", "unused", "unused", "unused",
					"dfllCPU_out" };

static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
					"pll_p", "pll_p_out4", "unused",
					"unused", "pll_x", "unused", "unused",
					"unused", "unused", "unused", "unused",
					"dfllCPU_out" };

static const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {
	.gen = gen5,
	.sclk_parents = sclk_parents_gen5,
	.cclk_g_parents = cclk_g_parents_gen5,
	.cclk_lp_parents = cclk_lp_parents_gen5,
	.num_sclk_parents = ARRAY_SIZE(sclk_parents_gen5),
	.num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents_gen5),
	.num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents_gen5),
};

static void __init tegra_sclk_init(void __iomem *clk_base,
				struct tegra_clk *tegra_clks,
				const struct tegra_super_gen_info *gen_info)
{
	struct clk *clk;
	struct clk **dt_clk;

	/* SCLK_MUX */
	dt_clk = tegra_lookup_dt_id(tegra_clk_sclk_mux, tegra_clks);
	if (dt_clk) {
		clk = tegra_clk_register_super_mux("sclk_mux",
						gen_info->sclk_parents,
						gen_info->num_sclk_parents,
						CLK_SET_RATE_PARENT,
						clk_base + SCLK_BURST_POLICY,
						0, 4, 0, 0, NULL);
		*dt_clk = clk;


		/* SCLK */
		dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
		if (dt_clk) {
			clk = clk_register_divider(NULL, "sclk", "sclk_mux",
						CLK_IS_CRITICAL,
						clk_base + SCLK_DIVIDER, 0, 8,
						0, &sysrate_lock);
			*dt_clk = clk;
		}
	} else {
		/* SCLK */

Annotation

Implementation Notes