drivers/clk/tegra/clk-tegra124-dfll-fcpu.c

Source file repositories/reference/linux-study-clean/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
Extension
.c
Size
20254 bytes
Lines
750
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dfll_fcpu_data {
	const unsigned long *cpu_max_freq_table;
	unsigned int cpu_max_freq_table_size;
	const struct cvb_table *cpu_cvb_tables;
	unsigned int cpu_cvb_tables_size;
};

/* Maximum CPU frequency, indexed by CPU speedo id */
static const unsigned long tegra114_cpu_max_freq_table[] = {
	[0] = 2040000000UL,
	[1] = 1810500000UL,
	[2] = 1912500000UL,
	[3] = 1810500000UL,
};

#define T114_CPU_CVB_TABLE \
	.min_millivolts = 1000, \
	.max_millivolts = 1320, \
	.speedo_scale = 100,    \
	.voltage_scale = 1000,  \
	.entries = {            \
		{  306000000UL, { 2190643, -141851, 3576 } }, \
		{  408000000UL, { 2250968, -144331, 3576 } }, \
		{  510000000UL, { 2313333, -146811, 3576 } }, \
		{  612000000UL, { 2377738, -149291, 3576 } }, \
		{  714000000UL, { 2444183, -151771, 3576 } }, \
		{  816000000UL, { 2512669, -154251, 3576 } }, \
		{  918000000UL, { 2583194, -156731, 3576 } }, \
		{ 1020000000UL, { 2655759, -159211, 3576 } }, \
		{ 1122000000UL, { 2730365, -161691, 3576 } }, \
		{ 1224000000UL, { 2807010, -164171, 3576 } }, \
		{ 1326000000UL, { 2885696, -166651, 3576 } }, \
		{ 1428000000UL, { 2966422, -169131, 3576 } }, \
		{ 1530000000UL, { 3049183, -171601, 3576 } }, \
		{ 1606500000UL, { 3112179, -173451, 3576 } }, \
		{ 1708500000UL, { 3198504, -175931, 3576 } }, \
		{ 1810500000UL, { 3304747, -179126, 3576 } }, \
		{ 1912500000UL, { 3395401, -181606, 3576 } }, \
		{          0UL, {       0,       0,    0 } }, \
	}, \
	.cpu_dfll_data = {      \
		.tune0_low = 0x00b0039d,          \
		.tune0_high = 0x00b0009d,         \
		.tune1 = 0x0000001f,              \
		.tune_high_min_millivolts = 1050, \
	}

static const struct cvb_table tegra114_cpu_cvb_tables[] = {
	{
		.speedo_id = 0,
		.process_id = -1,
		.min_millivolts = 1000,
		.max_millivolts = 1250,
		.speedo_scale = 100,
		.voltage_scale = 100,
		.entries = {
			{  306000000UL, { 107330, -1569,   0 } },
			{  408000000UL, { 111250, -1666,   0 } },
			{  510000000UL, { 110000, -1460,   0 } },
			{  612000000UL, { 117290, -1745,   0 } },
			{  714000000UL, { 122700, -1910,   0 } },
			{  816000000UL, { 125620, -1945,   0 } },
			{  918000000UL, { 130560, -2076,   0 } },
			{ 1020000000UL, { 137280, -2303,   0 } },
			{ 1122000000UL, { 146440, -2660,   0 } },
			{ 1224000000UL, { 152190, -2825,   0 } },
			{ 1326000000UL, { 157520, -2953,   0 } },
			{ 1428000000UL, { 166100, -3261,   0 } },
			{ 1530000000UL, { 176410, -3647,   0 } },
			{ 1632000000UL, { 189620, -4186,   0 } },
			{ 1734000000UL, { 203190, -4725,   0 } },
			{ 1836000000UL, { 222670, -5573,   0 } },
			{ 1938000000UL, { 256210, -7165,   0 } },
			{ 2040000000UL, { 250050, -6544,   0 } },
			{          0UL, {      0,     0,   0 } },
		},
		.cpu_dfll_data = {
			.tune0_low = 0x00b0019d,
			.tune0_high = 0x00b0019d,
			.tune1 = 0x0000001f,
			.tune_high_min_millivolts = 1000,
		}
	},
	{
		.speedo_id = 1,
		.process_id = -1,
		T114_CPU_CVB_TABLE
	},
	{
		.speedo_id = 2,

Annotation

Implementation Notes