drivers/clk/tegra/clk-tegra20.c

Source file repositories/reference/linux-study-clean/drivers/clk/tegra/clk-tegra20.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/tegra/clk-tegra20.c
Extension
.c
Size
41984 bytes
Lines
1207
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 */

#include <linux/io.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/clk/tegra.h>
#include <linux/delay.h>
#include <dt-bindings/clock/tegra20-car.h>

#include "clk.h"
#include "clk-id.h"

#define MISC_CLK_ENB 0x48

#define OSC_CTRL 0x50
#define OSC_CTRL_OSC_FREQ_MASK (3u<<30)
#define OSC_CTRL_OSC_FREQ_13MHZ (0u<<30)
#define OSC_CTRL_OSC_FREQ_19_2MHZ (1u<<30)
#define OSC_CTRL_OSC_FREQ_12MHZ (2u<<30)
#define OSC_CTRL_OSC_FREQ_26MHZ (3u<<30)
#define OSC_CTRL_MASK (0x3f2u | OSC_CTRL_OSC_FREQ_MASK)

#define OSC_CTRL_PLL_REF_DIV_MASK	(3u<<28)
#define OSC_CTRL_PLL_REF_DIV_1		(0u<<28)
#define OSC_CTRL_PLL_REF_DIV_2		(1u<<28)
#define OSC_CTRL_PLL_REF_DIV_4		(2u<<28)

#define OSC_FREQ_DET 0x58
#define OSC_FREQ_DET_TRIG (1u<<31)

#define OSC_FREQ_DET_STATUS 0x5c
#define OSC_FREQ_DET_BUSYu (1<<31)
#define OSC_FREQ_DET_CNT_MASK 0xFFFFu

#define TEGRA20_CLK_PERIPH_BANKS	3

#define PLLS_BASE 0xf0
#define PLLS_MISC 0xf4
#define PLLC_BASE 0x80
#define PLLC_MISC 0x8c
#define PLLM_BASE 0x90
#define PLLM_MISC 0x9c
#define PLLP_BASE 0xa0
#define PLLP_MISC 0xac
#define PLLA_BASE 0xb0
#define PLLA_MISC 0xbc
#define PLLU_BASE 0xc0
#define PLLU_MISC 0xcc
#define PLLD_BASE 0xd0
#define PLLD_MISC 0xdc
#define PLLX_BASE 0xe0
#define PLLX_MISC 0xe4
#define PLLE_BASE 0xe8
#define PLLE_MISC 0xec

#define PLL_BASE_LOCK BIT(27)
#define PLLE_MISC_LOCK BIT(11)

#define PLL_MISC_LOCK_ENABLE 18
#define PLLDU_MISC_LOCK_ENABLE 22
#define PLLE_MISC_LOCK_ENABLE 9

#define PLLC_OUT 0x84
#define PLLM_OUT 0x94
#define PLLP_OUTA 0xa4
#define PLLP_OUTB 0xa8
#define PLLA_OUT 0xb4

#define CCLK_BURST_POLICY 0x20
#define SUPER_CCLK_DIVIDER 0x24
#define SCLK_BURST_POLICY 0x28
#define SUPER_SCLK_DIVIDER 0x2c
#define CLK_SYSTEM_RATE 0x30

#define CCLK_BURST_POLICY_SHIFT	28
#define CCLK_RUN_POLICY_SHIFT	4
#define CCLK_IDLE_POLICY_SHIFT	0
#define CCLK_IDLE_POLICY	1
#define CCLK_RUN_POLICY		2
#define CCLK_BURST_POLICY_PLLX	8

#define CLK_SOURCE_I2S1 0x100
#define CLK_SOURCE_I2S2 0x104

Annotation

Implementation Notes