drivers/clk/tegra/clk-tegra210-emc.c

Source file repositories/reference/linux-study-clean/drivers/clk/tegra/clk-tegra210-emc.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/tegra/clk-tegra210-emc.c
Extension
.c
Size
9182 bytes
Lines
380
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct tegra210_clk_emc {
	struct clk_hw hw;
	void __iomem *regs;

	struct tegra210_clk_emc_provider *provider;

	struct clk *parents[8];
};

static inline struct tegra210_clk_emc *
to_tegra210_clk_emc(struct clk_hw *hw)
{
	return container_of(hw, struct tegra210_clk_emc, hw);
}

static const char *tegra210_clk_emc_parents[] = {
	"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb_ud",
	"pll_mb", "pll_p_ud",
};

static u8 tegra210_clk_emc_get_parent(struct clk_hw *hw)
{
	struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
	u32 value;
	u8 src;

	value = readl_relaxed(emc->regs + CLK_SOURCE_EMC);
	src = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, value);

	return src;
}

static unsigned long tegra210_clk_emc_recalc_rate(struct clk_hw *hw,
						  unsigned long parent_rate)
{
	struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
	u32 value, div;

	/*
	 * CCF assumes that neither the parent nor its rate will change during
	 * ->set_rate(), so the parent rate passed in here was cached from the
	 * parent before the ->set_rate() call.
	 *
	 * This can lead to wrong results being reported for the EMC clock if
	 * the parent and/or parent rate have changed as part of the EMC rate
	 * change sequence. Fix this by overriding the parent clock with what
	 * we know to be the correct value after the rate change.
	 */
	parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));

	value = readl_relaxed(emc->regs + CLK_SOURCE_EMC);

	div = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_DIVISOR, value);
	div += 2;

	return DIV_ROUND_UP(parent_rate * 2, div);
}

static int tegra210_clk_emc_determine_rate(struct clk_hw *hw,
					   struct clk_rate_request *req)
{
	struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
	struct tegra210_clk_emc_provider *provider = emc->provider;
	unsigned int i;

	if (!provider || !provider->configs || provider->num_configs == 0) {
		req->rate = clk_hw_get_rate(hw);

		return 0;
	}

	for (i = 0; i < provider->num_configs; i++) {
		if (provider->configs[i].rate >= req->rate) {
			req->rate = provider->configs[i].rate;

			return 0;
		}
	}

	req->rate = provider->configs[i - 1].rate;

	return 0;
}

static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc,
						u8 index)
{
	struct clk_hw *parent = clk_hw_get_parent_by_index(&emc->hw, index);
	const char *name = clk_hw_get_name(parent);

Annotation

Implementation Notes