drivers/clk/ti/clk-54xx.c
Source file repositories/reference/linux-study-clean/drivers/clk/ti/clk-54xx.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/ti/clk-54xx.c- Extension
.c- Size
- 23671 bytes
- Lines
- 659
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/list.hlinux/clk.hlinux/clkdev.hlinux/io.hlinux/clk/ti.hdt-bindings/clock/omap5.hclock.h
Detected Declarations
function omap5xxx_dt_clk_init
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP5 Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo (t-kristo@ti.com)
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/omap5.h>
#include "clock.h"
#define OMAP5_DPLL_ABE_DEFFREQ 98304000
/*
* OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
* states it must be at 960MHz
*/
#define OMAP5_DPLL_USB_DEFFREQ 960000000
static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
{ OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
{ OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" },
{ 0 },
};
static const char * const omap5_aess_fclk_parents[] __initconst = {
"abe_clk",
NULL,
};
static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = {
.max_div = 2,
};
static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
{ 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data },
{ 0 },
};
static const char * const omap5_dmic_gfclk_parents[] __initconst = {
"abe-clkctrl:0018:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
"abe_24m_fclk",
"dss_syc_gfclk_div",
"func_24m_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
"abe-clkctrl:0028:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
"abe-clkctrl:0030:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/list.h`, `linux/clk.h`, `linux/clkdev.h`, `linux/io.h`, `linux/clk/ti.h`, `dt-bindings/clock/omap5.h`, `clock.h`.
- Detected declarations: `function omap5xxx_dt_clk_init`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.