drivers/clk/ti/clock.h
Source file repositories/reference/linux-study-clean/drivers/clk/ti/clock.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/ti/clock.h- Extension
.h- Size
- 8668 bytes
- Lines
- 305
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct clk_omap_dividerstruct clk_omap_muxstruct ti_clkstruct ti_clk_muxstruct ti_clk_dividerstruct ti_clk_gatestruct ti_dt_clkstruct omap_clkctrl_div_datastruct omap_clkctrl_bit_datastruct omap_clkctrl_reg_datastruct omap_clkctrl_data
Annotated Snippet
struct clk_omap_divider {
struct clk_hw hw;
struct clk_omap_reg reg;
u8 shift;
u8 flags;
s8 latch;
u16 min;
u16 max;
u16 mask;
const struct clk_div_table *table;
u32 context;
};
#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
struct clk_omap_mux {
struct clk_hw hw;
struct clk_omap_reg reg;
u32 *table;
u32 mask;
u8 shift;
s8 latch;
u8 flags;
u8 saved_parent;
};
#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
enum {
TI_CLK_FIXED,
TI_CLK_MUX,
TI_CLK_DIVIDER,
TI_CLK_COMPOSITE,
TI_CLK_FIXED_FACTOR,
TI_CLK_GATE,
TI_CLK_DPLL,
};
/* Global flags */
#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
#define CLKF_SET_RATE_PARENT (1 << 2)
#define CLKF_OMAP3 (1 << 3)
#define CLKF_AM35XX (1 << 4)
/* Gate flags */
#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
#define CLKF_INTERFACE (1 << 6)
#define CLKF_SSI (1 << 7)
#define CLKF_DSS (1 << 8)
#define CLKF_HSOTGUSB (1 << 9)
#define CLKF_WAIT (1 << 10)
#define CLKF_NO_WAIT (1 << 11)
#define CLKF_HSDIV (1 << 12)
#define CLKF_CLKDM (1 << 13)
/* DPLL flags */
#define CLKF_LOW_POWER_STOP (1 << 5)
#define CLKF_LOCK (1 << 6)
#define CLKF_LOW_POWER_BYPASS (1 << 7)
#define CLKF_PER (1 << 8)
#define CLKF_CORE (1 << 9)
#define CLKF_J_TYPE (1 << 10)
/* CLKCTRL flags */
#define CLKF_SW_SUP BIT(5)
#define CLKF_HW_SUP BIT(6)
#define CLKF_NO_IDLEST BIT(7)
#define CLKF_SOC_MASK GENMASK(11, 8)
#define CLKF_SOC_NONSEC BIT(8)
#define CLKF_SOC_DRA72 BIT(9)
#define CLKF_SOC_DRA74 BIT(10)
#define CLKF_SOC_DRA76 BIT(11)
#define CLK(dev, con, ck) \
{ \
.lk = { \
.dev_id = dev, \
.con_id = con, \
}, \
.clk = ck, \
}
struct ti_clk {
const char *name;
const char *clkdm_name;
int type;
void *data;
Annotation
- Detected declarations: `struct clk_omap_divider`, `struct clk_omap_mux`, `struct ti_clk`, `struct ti_clk_mux`, `struct ti_clk_divider`, `struct ti_clk_gate`, `struct ti_dt_clk`, `struct omap_clkctrl_div_data`, `struct omap_clkctrl_bit_data`, `struct omap_clkctrl_reg_data`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.