drivers/clk/uniphier/clk-uniphier.h
Source file repositories/reference/linux-study-clean/drivers/clk/uniphier/clk-uniphier.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/uniphier/clk-uniphier.h- Extension
.h- Size
- 4871 bytes
- Lines
- 161
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct clk_hwstruct devicestruct regmapstruct uniphier_clk_cpugear_datastruct uniphier_clk_fixed_factor_datastruct uniphier_clk_fixed_rate_datastruct uniphier_clk_gate_datastruct uniphier_clk_mux_datastruct uniphier_clk_dataenum uniphier_clk_type
Annotated Snippet
struct uniphier_clk_cpugear_data {
const char *parent_names[UNIPHIER_CLK_CPUGEAR_MAX_PARENTS];
unsigned int num_parents;
unsigned int regbase;
unsigned int mask;
};
struct uniphier_clk_fixed_factor_data {
const char *parent_name;
unsigned int mult;
unsigned int div;
};
struct uniphier_clk_fixed_rate_data {
unsigned long fixed_rate;
};
struct uniphier_clk_gate_data {
const char *parent_name;
unsigned int reg;
unsigned int bit;
};
struct uniphier_clk_mux_data {
const char *parent_names[UNIPHIER_CLK_MUX_MAX_PARENTS];
unsigned int num_parents;
unsigned int reg;
unsigned int masks[UNIPHIER_CLK_MUX_MAX_PARENTS];
unsigned int vals[UNIPHIER_CLK_MUX_MAX_PARENTS];
};
struct uniphier_clk_data {
const char *name;
enum uniphier_clk_type type;
int idx;
union {
struct uniphier_clk_cpugear_data cpugear;
struct uniphier_clk_fixed_factor_data factor;
struct uniphier_clk_fixed_rate_data rate;
struct uniphier_clk_gate_data gate;
struct uniphier_clk_mux_data mux;
} data;
};
#define UNIPHIER_CLK_CPUGEAR(_name, _idx, _regbase, _mask, \
_num_parents, ...) \
{ \
.name = (_name), \
.type = UNIPHIER_CLK_TYPE_CPUGEAR, \
.idx = (_idx), \
.data.cpugear = { \
.parent_names = { __VA_ARGS__ }, \
.num_parents = (_num_parents), \
.regbase = (_regbase), \
.mask = (_mask) \
}, \
}
#define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div) \
{ \
.name = (_name), \
.type = UNIPHIER_CLK_TYPE_FIXED_FACTOR, \
.idx = (_idx), \
.data.factor = { \
.parent_name = (_parent), \
.mult = (_mult), \
.div = (_div), \
}, \
}
#define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \
{ \
.name = (_name), \
.type = UNIPHIER_CLK_TYPE_GATE, \
.idx = (_idx), \
.data.gate = { \
.parent_name = (_parent), \
.reg = (_reg), \
.bit = (_bit), \
}, \
}
#define UNIPHIER_CLK_DIV(parent, div) \
UNIPHIER_CLK_FACTOR(parent "/" #div, -1, parent, 1, div)
#define UNIPHIER_CLK_DIV2(parent, div0, div1) \
UNIPHIER_CLK_DIV(parent, div0), \
UNIPHIER_CLK_DIV(parent, div1)
#define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \
Annotation
- Detected declarations: `struct clk_hw`, `struct device`, `struct regmap`, `struct uniphier_clk_cpugear_data`, `struct uniphier_clk_fixed_factor_data`, `struct uniphier_clk_fixed_rate_data`, `struct uniphier_clk_gate_data`, `struct uniphier_clk_mux_data`, `struct uniphier_clk_data`, `enum uniphier_clk_type`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.