drivers/clk/ux500/reset-prcc.c

Source file repositories/reference/linux-study-clean/drivers/clk/ux500/reset-prcc.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/ux500/reset-prcc.c
Extension
.c
Size
4871 bytes
Lines
182
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Reset controller portions for the U8500 PRCC
 * Copyright (C) 2021 Linus Walleij <linus.walleij@linaro.org>
 */
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/types.h>
#include <linux/reset-controller.h>
#include <linux/bits.h>
#include <linux/delay.h>

#include "prcc.h"
#include "reset-prcc.h"

#define to_u8500_prcc_reset(p) container_of((p), struct u8500_prcc_reset, rcdev)

/* This macro flattens the 2-dimensional PRCC numberspace */
#define PRCC_RESET_LINE(prcc_num, bit) \
	(((prcc_num) * PRCC_PERIPHS_PER_CLUSTER) + (bit))

/*
 * Reset registers in each PRCC - the reset lines are active low
 * so what you need to do is write a bit for the peripheral you
 * want to put into reset into the CLEAR register, this will assert
 * the reset by pulling the line low. SET take the device out of
 * reset. The status reflects the actual state of the line.
 */
#define PRCC_K_SOFTRST_SET		0x018
#define PRCC_K_SOFTRST_CLEAR		0x01c
#define PRCC_K_RST_STATUS		0x020

static int prcc_num_to_index(unsigned int num)
{
	switch (num) {
	case 1:
		return CLKRST1_INDEX;
	case 2:
		return CLKRST2_INDEX;
	case 3:
		return CLKRST3_INDEX;
	case 5:
		return CLKRST5_INDEX;
	case 6:
		return CLKRST6_INDEX;
	}
	return -EINVAL;
}

static void __iomem *u8500_prcc_reset_base(struct u8500_prcc_reset *ur,
					   unsigned long id)
{
	unsigned int prcc_num, index;

	prcc_num = id / PRCC_PERIPHS_PER_CLUSTER;
	index = prcc_num_to_index(prcc_num);

	if (index >= ARRAY_SIZE(ur->base))
		return NULL;

	return ur->base[index];
}

static int u8500_prcc_reset(struct reset_controller_dev *rcdev,
			    unsigned long id)
{
	struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev);
	void __iomem *base = u8500_prcc_reset_base(ur, id);
	unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER;

	pr_debug("PRCC cycle reset id %lu, bit %u\n", id, bit);

	/*
	 * Assert reset and then release it. The one microsecond
	 * delay is found in the vendor reference code.
	 */
	writel(BIT(bit), base + PRCC_K_SOFTRST_CLEAR);
	udelay(1);
	writel(BIT(bit), base + PRCC_K_SOFTRST_SET);
	udelay(1);

	return 0;
}

static int u8500_prcc_reset_assert(struct reset_controller_dev *rcdev,
				   unsigned long id)
{

Annotation

Implementation Notes