drivers/clk/visconti/clkc-tmpv770x.c

Source file repositories/reference/linux-study-clean/drivers/clk/visconti/clkc-tmpv770x.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/visconti/clkc-tmpv770x.c
Extension
.c
Size
12939 bytes
Lines
367
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Toshiba Visconti clock controller
 *
 * Copyright (c) 2021 TOSHIBA CORPORATION
 * Copyright (c) 2021 Toshiba Electronic Devices & Storage Corporation
 *
 * Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
 */

#include <linux/clk-provider.h>
#include <linux/platform_device.h>

#include <dt-bindings/clock/toshiba,tmpv770x.h>
#include <dt-bindings/reset/toshiba,tmpv770x.h>

#include "clkc.h"
#include "reset.h"

/* Must be equal to the last clock/reset ID increased by one */
#define CLKS_NR	(TMPV770X_CLK_VIIFBS1_PROC + 1)
#define RESETS_NR	(TMPV770X_RESET_VIIFBS1_L1ISP + 1)

static DEFINE_SPINLOCK(tmpv770x_clk_lock);
static DEFINE_SPINLOCK(tmpv770x_rst_lock);

static const struct clk_parent_data clks_parent_data[] = {
	{ .fw_name = "pipll1", .name = "pipll1", },
};

static const struct clk_parent_data pietherplls_parent_data[] = {
	{ .fw_name = "pietherpll", .name = "pietherpll", },
};

static const struct clk_parent_data pidnnplls_parent_data[] = {
	{ .fw_name = "pidnnpll", .name = "pidnnpll", },
};

static const struct visconti_fixed_clk fixed_clk_tables[] = {
	/* PLL1 */
	/* PICMPT0/1, PITSC, PIUWDT, PISWDT, PISBUS, PIPMU, PIGPMU, PITMU */
	/* PIEMM, PIMISC, PIGCOMM, PIDCOMM, PIMBUS, PIGPIO, PIPGM */
	{ TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, },
	/* PISBUS */
	{ TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, },
	/* PICOBUS_CLK */
	{ TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, },
	/* PIDNNPLL */
	/* CONN_CLK, PIMBUS, PICRC0/1 */
	{ TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, },
	{ TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, },
	{ TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, },
};

static const struct visconti_clk_gate_table pietherpll_clk_gate_tables[] = {
	/* pietherpll */
	{ TMPV770X_CLK_PIETHER_2P5M, "piether_2p5m",
		pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data),
		CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200,
		TMPV770X_RESET_PIETHER_2P5M, },
	{ TMPV770X_CLK_PIETHER_25M, "piether_25m",
		pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data),
		CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20,
		TMPV770X_RESET_PIETHER_25M, },
	{ TMPV770X_CLK_PIETHER_50M, "piether_50m",
		pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data),
		CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10,
		TMPV770X_RESET_PIETHER_50M, },
	{ TMPV770X_CLK_PIETHER_125M, "piether_125m",
		pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data),
		CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4,
		TMPV770X_RESET_PIETHER_125M, },
};

static const struct visconti_clk_gate_table pidnnpll_clk_gate_tables[] = {
	{ TMPV770X_CLK_VIIFBS0, "viifbs0",
		pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
		0, 0x58, 0x158, 1, 1,
		NO_RESET, },
	{ TMPV770X_CLK_VIIFBS0_PROC, "viifbs0_proc",
		pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
		0, 0x58, 0x158, 18, 1,
		NO_RESET, },
	{ TMPV770X_CLK_VIIFBS0_L1ISP, "viifbs0_l1isp",
		pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
		0, 0x58, 0x158, 17, 1,
		NO_RESET, },
	{ TMPV770X_CLK_VIIFBS0_L2ISP, "viifbs0_l2isp",
		pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
		0, 0x58, 0x158, 16, 1,

Annotation

Implementation Notes