drivers/clk/x86/clk-lgm.c

Source file repositories/reference/linux-study-clean/drivers/clk/x86/clk-lgm.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/x86/clk-lgm.c
Extension
.c
Size
15908 bytes
Lines
480
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020-2022 MaxLinear, Inc.
 * Copyright (C) 2020 Intel Corporation.
 * Zhu Yixin <yzhu@maxlinear.com>
 * Rahul Tanwar <rtanwar@maxlinear.com>
 */
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/intel,lgm-clk.h>
#include "clk-cgu.h"

#define PLL_DIV_WIDTH		4
#define PLL_DDIV_WIDTH		3

/* Gate0 clock shift */
#define G_C55_SHIFT		7
#define G_QSPI_SHIFT		9
#define G_EIP197_SHIFT		11
#define G_VAULT130_SHIFT	12
#define G_TOE_SHIFT		13
#define G_SDXC_SHIFT		14
#define G_EMMC_SHIFT		15
#define G_SPIDBG_SHIFT		17
#define G_DMA3_SHIFT		28

/* Gate1 clock shift */
#define G_DMA0_SHIFT		0
#define G_LEDC0_SHIFT		1
#define G_LEDC1_SHIFT		2
#define G_I2S0_SHIFT		3
#define G_I2S1_SHIFT		4
#define G_EBU_SHIFT		5
#define G_PWM_SHIFT		6
#define G_I2C0_SHIFT		7
#define G_I2C1_SHIFT		8
#define G_I2C2_SHIFT		9
#define G_I2C3_SHIFT		10

#define G_SSC0_SHIFT		12
#define G_SSC1_SHIFT		13
#define G_SSC2_SHIFT		14
#define G_SSC3_SHIFT		15

#define G_GPTC0_SHIFT		17
#define G_GPTC1_SHIFT		18
#define G_GPTC2_SHIFT		19
#define G_GPTC3_SHIFT		20

#define G_ASC0_SHIFT		22
#define G_ASC1_SHIFT		23
#define G_ASC2_SHIFT		24
#define G_ASC3_SHIFT		25

#define G_PCM0_SHIFT		27
#define G_PCM1_SHIFT		28
#define G_PCM2_SHIFT		29

/* Gate2 clock shift */
#define G_PCIE10_SHIFT		1
#define G_PCIE11_SHIFT		2
#define G_PCIE30_SHIFT		3
#define G_PCIE31_SHIFT		4
#define G_PCIE20_SHIFT		5
#define G_PCIE21_SHIFT		6
#define G_PCIE40_SHIFT		7
#define G_PCIE41_SHIFT		8

#define G_XPCS0_SHIFT		10
#define G_XPCS1_SHIFT		11
#define G_XPCS2_SHIFT		12
#define G_XPCS3_SHIFT		13
#define G_SATA0_SHIFT		14
#define G_SATA1_SHIFT		15
#define G_SATA2_SHIFT		16
#define G_SATA3_SHIFT		17

/* Gate3 clock shift */
#define G_ARCEM4_SHIFT		0
#define G_IDMAR1_SHIFT		2
#define G_IDMAT0_SHIFT		3
#define G_IDMAT1_SHIFT		4
#define G_IDMAT2_SHIFT		5

#define G_PPV4_SHIFT		8
#define G_GSWIPO_SHIFT		9
#define G_CQEM_SHIFT		10
#define G_XPCS5_SHIFT		14

Annotation

Implementation Notes