drivers/clk/xilinx/xlnx_vcu.c
Source file repositories/reference/linux-study-clean/drivers/clk/xilinx/xlnx_vcu.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/xilinx/xlnx_vcu.c- Extension
.c- Size
- 20172 bytes
- Lines
- 772
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/clk.hlinux/clk-provider.hlinux/device.hlinux/errno.hlinux/gpio/consumer.hlinux/io.hlinux/mfd/syscon.hlinux/mfd/syscon/xlnx-vcu.hlinux/module.hlinux/mod_devicetable.hlinux/platform_device.hlinux/regmap.hdt-bindings/clock/xlnx-vcu.h
Detected Declarations
struct xvcu_devicestruct xvcu_pll_cfgstruct vcu_pllfunction xvcu_readfunction xvcu_writefunction xvcu_pll_wait_for_lockfunction xvcu_pll_set_divfunction xvcu_pll_determine_ratefunction xvcu_pll_recalc_ratefunction xvcu_pll_set_ratefunction xvcu_pll_enablefunction xvcu_pll_disablefunction xvcu_clk_hw_unregister_leaffunction xvcu_register_clock_providerfunction xvcu_unregister_clock_providerfunction xvcu_probefunction xvcu_remove
Annotated Snippet
struct xvcu_device {
struct device *dev;
struct clk *pll_ref;
struct clk *aclk;
struct gpio_desc *reset_gpio;
struct regmap *logicore_reg_ba;
void __iomem *vcu_slcr_ba;
struct clk_hw *pll;
struct clk_hw *pll_post;
struct clk_hw_onecell_data *clk_data;
};
static const struct regmap_config vcu_settings_regmap_config = {
.name = "regmap",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = 0xfff,
.cache_type = REGCACHE_NONE,
};
/**
* struct xvcu_pll_cfg - Helper data
* @fbdiv: The integer portion of the feedback divider to the PLL
* @cp: PLL charge pump control
* @res: PLL loop filter resistor control
* @lfhf: PLL loop filter high frequency capacitor control
* @lock_dly: Lock circuit configuration settings for lock windowsize
* @lock_cnt: Lock circuit counter setting
*/
struct xvcu_pll_cfg {
u32 fbdiv;
u32 cp;
u32 res;
u32 lfhf;
u32 lock_dly;
u32 lock_cnt;
};
static const struct xvcu_pll_cfg xvcu_pll_cfg[] = {
{ 25, 3, 10, 3, 63, 1000 },
{ 26, 3, 10, 3, 63, 1000 },
{ 27, 4, 6, 3, 63, 1000 },
{ 28, 4, 6, 3, 63, 1000 },
{ 29, 4, 6, 3, 63, 1000 },
{ 30, 4, 6, 3, 63, 1000 },
{ 31, 6, 1, 3, 63, 1000 },
{ 32, 6, 1, 3, 63, 1000 },
{ 33, 4, 10, 3, 63, 1000 },
{ 34, 5, 6, 3, 63, 1000 },
{ 35, 5, 6, 3, 63, 1000 },
{ 36, 5, 6, 3, 63, 1000 },
{ 37, 5, 6, 3, 63, 1000 },
{ 38, 5, 6, 3, 63, 975 },
{ 39, 3, 12, 3, 63, 950 },
{ 40, 3, 12, 3, 63, 925 },
{ 41, 3, 12, 3, 63, 900 },
{ 42, 3, 12, 3, 63, 875 },
{ 43, 3, 12, 3, 63, 850 },
{ 44, 3, 12, 3, 63, 850 },
{ 45, 3, 12, 3, 63, 825 },
{ 46, 3, 12, 3, 63, 800 },
{ 47, 3, 12, 3, 63, 775 },
{ 48, 3, 12, 3, 63, 775 },
{ 49, 3, 12, 3, 63, 750 },
{ 50, 3, 12, 3, 63, 750 },
{ 51, 3, 2, 3, 63, 725 },
{ 52, 3, 2, 3, 63, 700 },
{ 53, 3, 2, 3, 63, 700 },
{ 54, 3, 2, 3, 63, 675 },
{ 55, 3, 2, 3, 63, 675 },
{ 56, 3, 2, 3, 63, 650 },
{ 57, 3, 2, 3, 63, 650 },
{ 58, 3, 2, 3, 63, 625 },
{ 59, 3, 2, 3, 63, 625 },
{ 60, 3, 2, 3, 63, 625 },
{ 61, 3, 2, 3, 63, 600 },
{ 62, 3, 2, 3, 63, 600 },
{ 63, 3, 2, 3, 63, 600 },
{ 64, 3, 2, 3, 63, 600 },
{ 65, 3, 2, 3, 63, 600 },
{ 66, 3, 2, 3, 63, 600 },
{ 67, 3, 2, 3, 63, 600 },
{ 68, 3, 2, 3, 63, 600 },
{ 69, 3, 2, 3, 63, 600 },
{ 70, 3, 2, 3, 63, 600 },
{ 71, 3, 2, 3, 63, 600 },
{ 72, 3, 2, 3, 63, 600 },
{ 73, 3, 2, 3, 63, 600 },
{ 74, 3, 2, 3, 63, 600 },
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/clk.h`, `linux/clk-provider.h`, `linux/device.h`, `linux/errno.h`, `linux/gpio/consumer.h`, `linux/io.h`, `linux/mfd/syscon.h`.
- Detected declarations: `struct xvcu_device`, `struct xvcu_pll_cfg`, `struct vcu_pll`, `function xvcu_read`, `function xvcu_write`, `function xvcu_pll_wait_for_lock`, `function xvcu_pll_set_div`, `function xvcu_pll_determine_rate`, `function xvcu_pll_recalc_rate`, `function xvcu_pll_set_rate`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.