drivers/clk/zynqmp/clk-gate-zynqmp.c

Source file repositories/reference/linux-study-clean/drivers/clk/zynqmp/clk-gate-zynqmp.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/zynqmp/clk-gate-zynqmp.c
Extension
.c
Size
3383 bytes
Lines
144
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct zynqmp_clk_gate {
	struct clk_hw hw;
	u8 flags;
	u32 clk_id;
};

#define to_zynqmp_clk_gate(_hw) container_of(_hw, struct zynqmp_clk_gate, hw)

/**
 * zynqmp_clk_gate_enable() - Enable clock
 * @hw:		handle between common and hardware-specific interfaces
 *
 * Return: 0 on success else error code
 */
static int zynqmp_clk_gate_enable(struct clk_hw *hw)
{
	struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
	const char *clk_name = clk_hw_get_name(hw);
	u32 clk_id = gate->clk_id;
	int ret;

	ret = zynqmp_pm_clock_enable(clk_id);

	if (ret)
		pr_debug("%s() clock enable failed for %s (id %d), ret = %d\n",
			 __func__, clk_name, clk_id, ret);

	return ret;
}

/*
 * zynqmp_clk_gate_disable() - Disable clock
 * @hw:		handle between common and hardware-specific interfaces
 */
static void zynqmp_clk_gate_disable(struct clk_hw *hw)
{
	struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
	const char *clk_name = clk_hw_get_name(hw);
	u32 clk_id = gate->clk_id;
	int ret;

	ret = zynqmp_pm_clock_disable(clk_id);

	if (ret)
		pr_debug("%s() clock disable failed for %s (id %d), ret = %d\n",
			 __func__, clk_name, clk_id, ret);
}

/**
 * zynqmp_clk_gate_is_enabled() - Check clock state
 * @hw:		handle between common and hardware-specific interfaces
 *
 * Return: 1 if enabled, 0 if disabled else error code
 */
static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw)
{
	struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
	const char *clk_name = clk_hw_get_name(hw);
	u32 clk_id = gate->clk_id;
	int state, ret;

	ret = zynqmp_pm_clock_getstate(clk_id, &state);
	if (ret) {
		pr_debug("%s() clock get state failed for %s, ret = %d\n",
			 __func__, clk_name, ret);
		return -EIO;
	}

	return state ? 1 : 0;
}

static const struct clk_ops zynqmp_clk_gate_ops = {
	.enable = zynqmp_clk_gate_enable,
	.disable = zynqmp_clk_gate_disable,
	.is_enabled = zynqmp_clk_gate_is_enabled,
};

/**
 * zynqmp_clk_register_gate() - Register a gate clock with the clock framework
 * @name:		Name of this clock
 * @clk_id:		Id of this clock
 * @parents:		Name of this clock's parents
 * @num_parents:	Number of parents
 * @nodes:		Clock topology node
 *
 * Return: clock hardware of the registered clock gate
 */
struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
					const char * const *parents,
					u8 num_parents,

Annotation

Implementation Notes