drivers/clocksource/timer-goldfish.c
Source file repositories/reference/linux-study-clean/drivers/clocksource/timer-goldfish.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clocksource/timer-goldfish.c- Extension
.c- Size
- 3643 bytes
- Lines
- 154
- Domain
- Driver Families
- Bucket
- drivers/clocksource
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/interrupt.hlinux/ioport.hlinux/clocksource.hlinux/clockchips.hlinux/module.hlinux/slab.hlinux/goldfish.hclocksource/timer-goldfish.h
Detected Declarations
struct goldfish_timerfunction goldfish_timer_readfunction goldfish_timer_set_oneshotfunction goldfish_timer_shutdownfunction goldfish_timer_next_eventfunction goldfish_timer_irqfunction goldfish_timer_init
Annotated Snippet
struct goldfish_timer {
struct clocksource cs;
struct clock_event_device ced;
struct resource res;
void __iomem *base;
};
static struct goldfish_timer *ced_to_gf(struct clock_event_device *ced)
{
return container_of(ced, struct goldfish_timer, ced);
}
static struct goldfish_timer *cs_to_gf(struct clocksource *cs)
{
return container_of(cs, struct goldfish_timer, cs);
}
static u64 goldfish_timer_read(struct clocksource *cs)
{
struct goldfish_timer *timerdrv = cs_to_gf(cs);
void __iomem *base = timerdrv->base;
u32 time_low, time_high;
u64 ticks;
/*
* time_low: get low bits of current time and update time_high
* time_high: get high bits of time at last time_low read
*/
time_low = gf_ioread32(base + TIMER_TIME_LOW);
time_high = gf_ioread32(base + TIMER_TIME_HIGH);
ticks = ((u64)time_high << 32) | time_low;
return ticks;
}
static int goldfish_timer_set_oneshot(struct clock_event_device *evt)
{
struct goldfish_timer *timerdrv = ced_to_gf(evt);
void __iomem *base = timerdrv->base;
gf_iowrite32(0, base + TIMER_ALARM_HIGH);
gf_iowrite32(0, base + TIMER_ALARM_LOW);
gf_iowrite32(1, base + TIMER_IRQ_ENABLED);
return 0;
}
static int goldfish_timer_shutdown(struct clock_event_device *evt)
{
struct goldfish_timer *timerdrv = ced_to_gf(evt);
void __iomem *base = timerdrv->base;
gf_iowrite32(0, base + TIMER_IRQ_ENABLED);
return 0;
}
static int goldfish_timer_next_event(unsigned long delta,
struct clock_event_device *evt)
{
struct goldfish_timer *timerdrv = ced_to_gf(evt);
void __iomem *base = timerdrv->base;
u64 now;
now = goldfish_timer_read(&timerdrv->cs);
now += delta;
gf_iowrite32(upper_32_bits(now), base + TIMER_ALARM_HIGH);
gf_iowrite32(lower_32_bits(now), base + TIMER_ALARM_LOW);
return 0;
}
static irqreturn_t goldfish_timer_irq(int irq, void *dev_id)
{
struct goldfish_timer *timerdrv = dev_id;
struct clock_event_device *evt = &timerdrv->ced;
void __iomem *base = timerdrv->base;
gf_iowrite32(1, base + TIMER_CLEAR_INTERRUPT);
evt->event_handler(evt);
return IRQ_HANDLED;
}
int __init goldfish_timer_init(int irq, void __iomem *base)
{
Annotation
- Immediate include surface: `linux/interrupt.h`, `linux/ioport.h`, `linux/clocksource.h`, `linux/clockchips.h`, `linux/module.h`, `linux/slab.h`, `linux/goldfish.h`, `clocksource/timer-goldfish.h`.
- Detected declarations: `struct goldfish_timer`, `function goldfish_timer_read`, `function goldfish_timer_set_oneshot`, `function goldfish_timer_shutdown`, `function goldfish_timer_next_event`, `function goldfish_timer_irq`, `function goldfish_timer_init`.
- Atlas domain: Driver Families / drivers/clocksource.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.