drivers/clocksource/timer-gx6605s.c
Source file repositories/reference/linux-study-clean/drivers/clocksource/timer-gx6605s.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clocksource/timer-gx6605s.c- Extension
.c- Size
- 4091 bytes
- Lines
- 156
- Domain
- Driver Families
- Bucket
- drivers/clocksource
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/interrupt.hlinux/sched_clock.htimer-of.h
Detected Declarations
function gx6605s_timer_interruptfunction gx6605s_timer_set_oneshotfunction gx6605s_timer_set_next_eventfunction gx6605s_timer_shutdownfunction gx6605s_sched_clock_readfunction gx6605s_clkevt_initfunction gx6605s_clksrc_initfunction gx6605s_timer_init
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/sched_clock.h>
#include "timer-of.h"
#define CLKSRC_OFFSET 0x40
#define TIMER_STATUS 0x00
#define TIMER_VALUE 0x04
#define TIMER_CONTRL 0x10
#define TIMER_CONFIG 0x20
#define TIMER_DIV 0x24
#define TIMER_INI 0x28
#define GX6605S_STATUS_CLR BIT(0)
#define GX6605S_CONTRL_RST BIT(0)
#define GX6605S_CONTRL_START BIT(1)
#define GX6605S_CONFIG_EN BIT(0)
#define GX6605S_CONFIG_IRQ_EN BIT(1)
static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev)
{
struct clock_event_device *ce = dev;
void __iomem *base = timer_of_base(to_timer_of(ce));
writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS);
writel_relaxed(0, base + TIMER_INI);
ce->event_handler(ce);
return IRQ_HANDLED;
}
static int gx6605s_timer_set_oneshot(struct clock_event_device *ce)
{
void __iomem *base = timer_of_base(to_timer_of(ce));
/* reset and stop counter */
writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
/* enable with irq and start */
writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN,
base + TIMER_CONFIG);
return 0;
}
static int gx6605s_timer_set_next_event(unsigned long delta,
struct clock_event_device *ce)
{
void __iomem *base = timer_of_base(to_timer_of(ce));
/* use reset to pause timer */
writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
/* config next timeout value */
writel_relaxed(ULONG_MAX - delta, base + TIMER_INI);
writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
return 0;
}
static int gx6605s_timer_shutdown(struct clock_event_device *ce)
{
void __iomem *base = timer_of_base(to_timer_of(ce));
writel_relaxed(0, base + TIMER_CONTRL);
writel_relaxed(0, base + TIMER_CONFIG);
return 0;
}
static struct timer_of to = {
.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
.clkevt = {
.rating = 300,
.features = CLOCK_EVT_FEAT_DYNIRQ |
CLOCK_EVT_FEAT_ONESHOT,
.set_state_shutdown = gx6605s_timer_shutdown,
.set_state_oneshot = gx6605s_timer_set_oneshot,
.set_next_event = gx6605s_timer_set_next_event,
.cpumask = cpu_possible_mask,
},
.of_irq = {
.handler = gx6605s_timer_interrupt,
.flags = IRQF_TIMER | IRQF_IRQPOLL,
Annotation
- Immediate include surface: `linux/init.h`, `linux/interrupt.h`, `linux/sched_clock.h`, `timer-of.h`.
- Detected declarations: `function gx6605s_timer_interrupt`, `function gx6605s_timer_set_oneshot`, `function gx6605s_timer_set_next_event`, `function gx6605s_timer_shutdown`, `function gx6605s_sched_clock_read`, `function gx6605s_clkevt_init`, `function gx6605s_clksrc_init`, `function gx6605s_timer_init`.
- Atlas domain: Driver Families / drivers/clocksource.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.