drivers/clocksource/timer-imx-sysctr.c
Source file repositories/reference/linux-study-clean/drivers/clocksource/timer-imx-sysctr.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clocksource/timer-imx-sysctr.c- Extension
.c- Size
- 4529 bytes
- Lines
- 208
- Domain
- Driver Families
- Bucket
- drivers/clocksource
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/interrupt.hlinux/clockchips.hlinux/slab.htimer-of.h
Detected Declarations
struct sysctr_privatefunction sysctr_timer_enablefunction sysctr_irq_acknowledgefunction sysctr_read_counterfunction sysctr_set_next_eventfunction sysctr_set_state_oneshotfunction sysctr_set_state_shutdownfunction sysctr_timer_interruptfunction __sysctr_timer_initfunction sysctr_timer_initfunction sysctr_timer_imx95_init
Annotated Snippet
struct sysctr_private {
u32 cmpcr;
u32 lo_off;
u32 hi_off;
};
static void sysctr_timer_enable(struct clock_event_device *evt, bool enable)
{
struct timer_of *to = to_timer_of(evt);
struct sysctr_private *priv = to->private_data;
void __iomem *base = timer_of_base(to);
writel(enable ? priv->cmpcr | SYS_CTR_EN : priv->cmpcr, base + CMPCR);
}
static void sysctr_irq_acknowledge(struct clock_event_device *evt)
{
/*
* clear the enable bit(EN =0) will clear
* the status bit(ISTAT = 0), then the interrupt
* signal will be negated(acknowledged).
*/
sysctr_timer_enable(evt, false);
}
static inline u64 sysctr_read_counter(struct clock_event_device *evt)
{
struct timer_of *to = to_timer_of(evt);
struct sysctr_private *priv = to->private_data;
void __iomem *base = timer_of_base(to);
u32 cnt_hi, tmp_hi, cnt_lo;
do {
cnt_hi = readl_relaxed(base + priv->hi_off);
cnt_lo = readl_relaxed(base + priv->lo_off);
tmp_hi = readl_relaxed(base + priv->hi_off);
} while (tmp_hi != cnt_hi);
return ((u64) cnt_hi << 32) | cnt_lo;
}
static int sysctr_set_next_event(unsigned long delta,
struct clock_event_device *evt)
{
struct timer_of *to = to_timer_of(evt);
void __iomem *base = timer_of_base(to);
u32 cmp_hi, cmp_lo;
u64 next;
sysctr_timer_enable(evt, false);
next = sysctr_read_counter(evt);
next += delta;
cmp_hi = (next >> 32) & 0x00fffff;
cmp_lo = next & 0xffffffff;
writel_relaxed(cmp_hi, base + CMPCV_HI);
writel_relaxed(cmp_lo, base + CMPCV_LO);
sysctr_timer_enable(evt, true);
return 0;
}
static int sysctr_set_state_oneshot(struct clock_event_device *evt)
{
return 0;
}
static int sysctr_set_state_shutdown(struct clock_event_device *evt)
{
sysctr_timer_enable(evt, false);
return 0;
}
static irqreturn_t sysctr_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
sysctr_irq_acknowledge(evt);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct timer_of to_sysctr = {
Annotation
- Immediate include surface: `linux/interrupt.h`, `linux/clockchips.h`, `linux/slab.h`, `timer-of.h`.
- Detected declarations: `struct sysctr_private`, `function sysctr_timer_enable`, `function sysctr_irq_acknowledge`, `function sysctr_read_counter`, `function sysctr_set_next_event`, `function sysctr_set_state_oneshot`, `function sysctr_set_state_shutdown`, `function sysctr_timer_interrupt`, `function __sysctr_timer_init`, `function sysctr_timer_init`.
- Atlas domain: Driver Families / drivers/clocksource.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.