drivers/clocksource/timer-meson6.c

Source file repositories/reference/linux-study-clean/drivers/clocksource/timer-meson6.c

File Facts

System
Linux kernel
Corpus path
drivers/clocksource/timer-meson6.c
Extension
.c
Size
5915 bytes
Lines
213
Domain
Driver Families
Bucket
drivers/clocksource
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Amlogic Meson6 SoCs timer handling.
 *
 * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
 *
 * Based on code from Amlogic, Inc
 */

#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/sched_clock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#ifdef CONFIG_ARM
#include <linux/delay.h>
#endif

#define MESON_ISA_TIMER_MUX					0x00
#define MESON_ISA_TIMER_MUX_TIMERD_EN				BIT(19)
#define MESON_ISA_TIMER_MUX_TIMERC_EN				BIT(18)
#define MESON_ISA_TIMER_MUX_TIMERB_EN				BIT(17)
#define MESON_ISA_TIMER_MUX_TIMERA_EN				BIT(16)
#define MESON_ISA_TIMER_MUX_TIMERD_MODE				BIT(15)
#define MESON_ISA_TIMER_MUX_TIMERC_MODE				BIT(14)
#define MESON_ISA_TIMER_MUX_TIMERB_MODE				BIT(13)
#define MESON_ISA_TIMER_MUX_TIMERA_MODE				BIT(12)
#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK		GENMASK(10, 8)
#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_SYSTEM_CLOCK	0x0
#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US		0x1
#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_10US		0x2
#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_100US		0x3
#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1MS		0x4
#define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK		GENMASK(7, 6)
#define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK		GENMASK(5, 4)
#define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK		GENMASK(3, 2)
#define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK		GENMASK(1, 0)
#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US		0x0
#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_10US		0x1
#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_100US		0x0
#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1MS		0x3

#define MESON_ISA_TIMERA					0x04
#define MESON_ISA_TIMERB					0x08
#define MESON_ISA_TIMERC					0x0c
#define MESON_ISA_TIMERD					0x10
#define MESON_ISA_TIMERE					0x14

static void __iomem *timer_base;

#ifdef CONFIG_ARM
static unsigned long meson6_read_current_timer(void)
{
	return readl_relaxed(timer_base + MESON_ISA_TIMERE);
}

static struct delay_timer meson6_delay_timer = {
	.read_current_timer = meson6_read_current_timer,
	.freq = 1000 * 1000,
};
#endif

static u64 notrace meson6_timer_sched_read(void)
{
	return (u64)readl(timer_base + MESON_ISA_TIMERE);
}

static void meson6_clkevt_time_stop(void)
{
	u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);

	writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN,
	       timer_base + MESON_ISA_TIMER_MUX);
}

static void meson6_clkevt_time_setup(unsigned long delay)
{
	writel(delay, timer_base + MESON_ISA_TIMERA);
}

static void meson6_clkevt_time_start(bool periodic)
{
	u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);

Annotation

Implementation Notes