drivers/clocksource/timer-npcm7xx.c

Source file repositories/reference/linux-study-clean/drivers/clocksource/timer-npcm7xx.c

File Facts

System
Linux kernel
Corpus path
drivers/clocksource/timer-npcm7xx.c
Extension
.c
Size
6061 bytes
Lines
224
Domain
Driver Families
Bucket
drivers/clocksource
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2014-2018 Nuvoton Technologies tomer.maimon@nuvoton.com
 * All rights reserved.
 *
 * Copyright 2017 Google, Inc.
 */

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/clockchips.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include "timer-of.h"

/* Timers registers */
#define NPCM7XX_REG_TCSR0	0x0 /* Timer 0 Control and Status Register */
#define NPCM7XX_REG_TICR0	0x8 /* Timer 0 Initial Count Register */
#define NPCM7XX_REG_TCSR1	0x4 /* Timer 1 Control and Status Register */
#define NPCM7XX_REG_TICR1	0xc /* Timer 1 Initial Count Register */
#define NPCM7XX_REG_TDR1	0x14 /* Timer 1 Data Register */
#define NPCM7XX_REG_TISR	0x18 /* Timer Interrupt Status Register */

/* Timers control */
#define NPCM7XX_Tx_RESETINT		0x1f
#define NPCM7XX_Tx_PERIOD		BIT(27)
#define NPCM7XX_Tx_INTEN		BIT(29)
#define NPCM7XX_Tx_COUNTEN		BIT(30)
#define NPCM7XX_Tx_ONESHOT		0x0
#define NPCM7XX_Tx_OPER			GENMASK(28, 27)
#define NPCM7XX_Tx_MIN_PRESCALE		0x1
#define NPCM7XX_Tx_TDR_MASK_BITS	24
#define NPCM7XX_Tx_MAX_CNT		0xFFFFFF
#define NPCM7XX_T0_CLR_INT		0x1
#define NPCM7XX_Tx_CLR_CSR		0x0

/* Timers operating mode */
#define NPCM7XX_START_PERIODIC_Tx (NPCM7XX_Tx_PERIOD | NPCM7XX_Tx_COUNTEN | \
					NPCM7XX_Tx_INTEN | \
					NPCM7XX_Tx_MIN_PRESCALE)

#define NPCM7XX_START_ONESHOT_Tx (NPCM7XX_Tx_ONESHOT | NPCM7XX_Tx_COUNTEN | \
					NPCM7XX_Tx_INTEN | \
					NPCM7XX_Tx_MIN_PRESCALE)

#define NPCM7XX_START_Tx (NPCM7XX_Tx_COUNTEN | NPCM7XX_Tx_PERIOD | \
				NPCM7XX_Tx_MIN_PRESCALE)

#define NPCM7XX_DEFAULT_CSR (NPCM7XX_Tx_CLR_CSR | NPCM7XX_Tx_MIN_PRESCALE)

static int npcm7xx_timer_resume(struct clock_event_device *evt)
{
	struct timer_of *to = to_timer_of(evt);
	u32 val;

	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
	val |= NPCM7XX_Tx_COUNTEN;
	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);

	return 0;
}

static int npcm7xx_timer_shutdown(struct clock_event_device *evt)
{
	struct timer_of *to = to_timer_of(evt);
	u32 val;

	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
	val &= ~NPCM7XX_Tx_COUNTEN;
	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);

	return 0;
}

static int npcm7xx_timer_oneshot(struct clock_event_device *evt)
{
	struct timer_of *to = to_timer_of(evt);
	u32 val;

	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
	val &= ~NPCM7XX_Tx_OPER;
	val |= NPCM7XX_START_ONESHOT_Tx;
	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);

	return 0;

Annotation

Implementation Notes