drivers/comedi/drivers/multiq3.c

Source file repositories/reference/linux-study-clean/drivers/comedi/drivers/multiq3.c

File Facts

System
Linux kernel
Corpus path
drivers/comedi/drivers/multiq3.c
Extension
.c
Size
9288 bytes
Lines
342
Domain
Driver Families
Bucket
drivers/comedi
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * multiq3.c
 * Hardware driver for Quanser Consulting MultiQ-3 board
 *
 * COMEDI - Linux Control and Measurement Device Interface
 * Copyright (C) 1999 Anders Blomdell <anders.blomdell@control.lth.se>
 */

/*
 * Driver: multiq3
 * Description: Quanser Consulting MultiQ-3
 * Devices: [Quanser Consulting] MultiQ-3 (multiq3)
 * Author: Anders Blomdell <anders.blomdell@control.lth.se>
 * Status: works
 *
 * Configuration Options:
 *  [0] - I/O port base address
 *  [1] - IRQ (not used)
 *  [2] - Number of optional encoder chips installed on board
 *	  0 = none
 *	  1 = 2 inputs (Model -2E)
 *	  2 = 4 inputs (Model -4E)
 *	  3 = 6 inputs (Model -6E)
 *	  4 = 8 inputs (Model -8E)
 */

#include <linux/module.h>
#include <linux/comedi/comedidev.h>

/*
 * Register map
 */
#define MULTIQ3_DI_REG			0x00
#define MULTIQ3_DO_REG			0x00
#define MULTIQ3_AO_REG			0x02
#define MULTIQ3_AI_REG			0x04
#define MULTIQ3_AI_CONV_REG		0x04
#define MULTIQ3_STATUS_REG		0x06
#define MULTIQ3_STATUS_EOC		BIT(3)
#define MULTIQ3_STATUS_EOC_I		BIT(4)
#define MULTIQ3_CTRL_REG		0x06
#define MULTIQ3_CTRL_AO_CHAN(x)		(((x) & 0x7) << 0)
#define MULTIQ3_CTRL_RC(x)		(((x) & 0x3) << 0)
#define MULTIQ3_CTRL_AI_CHAN(x)		(((x) & 0x7) << 3)
#define MULTIQ3_CTRL_E_CHAN(x)		(((x) & 0x7) << 3)
#define MULTIQ3_CTRL_EN			BIT(6)
#define MULTIQ3_CTRL_AZ			BIT(7)
#define MULTIQ3_CTRL_CAL		BIT(8)
#define MULTIQ3_CTRL_SH			BIT(9)
#define MULTIQ3_CTRL_CLK		BIT(10)
#define MULTIQ3_CTRL_LD			(3 << 11)
#define MULTIQ3_CLK_REG			0x08
#define MULTIQ3_ENC_DATA_REG		0x0c
#define MULTIQ3_ENC_CTRL_REG		0x0e

/*
 * Encoder chip commands (from the programming manual)
 */
#define MULTIQ3_CLOCK_DATA		0x00	/* FCK frequency divider */
#define MULTIQ3_CLOCK_SETUP		0x18	/* xfer PR0 to PSC */
#define MULTIQ3_INPUT_SETUP		0x41	/* enable inputs A and B */
#define MULTIQ3_QUAD_X4			0x38	/* quadrature */
#define MULTIQ3_BP_RESET		0x01	/* reset byte pointer */
#define MULTIQ3_CNTR_RESET		0x02	/* reset counter */
#define MULTIQ3_TRSFRPR_CTR		0x08	/* xfre preset reg to counter */
#define MULTIQ3_TRSFRCNTR_OL		0x10	/* xfer CNTR to OL (x and y) */
#define MULTIQ3_EFLAG_RESET		0x06	/* reset E bit of flag reg */

/*
 * Limit on the number of optional encoder channels
 */
#define MULTIQ3_MAX_ENC_CHANS		8

static void multiq3_set_ctrl(struct comedi_device *dev, unsigned int bits)
{
	/*
	 * According to the programming manual, the SH and CLK bits should
	 * be kept high at all times.
	 */
	outw(MULTIQ3_CTRL_SH | MULTIQ3_CTRL_CLK | bits,
	     dev->iobase + MULTIQ3_CTRL_REG);
}

static int multiq3_ai_status(struct comedi_device *dev,
			     struct comedi_subdevice *s,
			     struct comedi_insn *insn,
			     unsigned long context)
{
	unsigned int status;

Annotation

Implementation Notes