drivers/comedi/drivers/ni_tio_internal.h

Source file repositories/reference/linux-study-clean/drivers/comedi/drivers/ni_tio_internal.h

File Facts

System
Linux kernel
Corpus path
drivers/comedi/drivers/ni_tio_internal.h
Extension
.h
Size
7390 bytes
Lines
177
Domain
Driver Families
Bucket
drivers/comedi
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _COMEDI_NI_TIO_INTERNAL_H
#define _COMEDI_NI_TIO_INTERNAL_H

#include "ni_tio.h"

#define NITIO_AUTO_INC_REG(x)		(NITIO_G0_AUTO_INC + (x))
#define GI_AUTO_INC_MASK		0xff
#define NITIO_CMD_REG(x)		(NITIO_G0_CMD + (x))
#define GI_ARM				BIT(0)
#define GI_SAVE_TRACE			BIT(1)
#define GI_LOAD				BIT(2)
#define GI_DISARM			BIT(4)
#define GI_CNT_DIR(x)			(((x) & 0x3) << 5)
#define GI_CNT_DIR_MASK			GI_CNT_DIR(3)
#define GI_WRITE_SWITCH			BIT(7)
#define GI_SYNC_GATE			BIT(8)
#define GI_LITTLE_BIG_ENDIAN		BIT(9)
#define GI_BANK_SWITCH_START		BIT(10)
#define GI_BANK_SWITCH_MODE		BIT(11)
#define GI_BANK_SWITCH_ENABLE		BIT(12)
#define GI_ARM_COPY			BIT(13)
#define GI_SAVE_TRACE_COPY		BIT(14)
#define GI_DISARM_COPY			BIT(15)
#define NITIO_HW_SAVE_REG(x)		(NITIO_G0_HW_SAVE + (x))
#define NITIO_SW_SAVE_REG(x)		(NITIO_G0_SW_SAVE + (x))
#define NITIO_MODE_REG(x)		(NITIO_G0_MODE + (x))
#define GI_GATING_MODE(x)		(((x) & 0x3) << 0)
#define GI_GATING_DISABLED		GI_GATING_MODE(0)
#define GI_LEVEL_GATING			GI_GATING_MODE(1)
#define GI_RISING_EDGE_GATING		GI_GATING_MODE(2)
#define GI_FALLING_EDGE_GATING		GI_GATING_MODE(3)
#define GI_GATING_MODE_MASK		GI_GATING_MODE(3)
#define GI_GATE_ON_BOTH_EDGES		BIT(2)
#define GI_EDGE_GATE_MODE(x)		(((x) & 0x3) << 3)
#define GI_EDGE_GATE_STARTS_STOPS	GI_EDGE_GATE_MODE(0)
#define GI_EDGE_GATE_STOPS_STARTS	GI_EDGE_GATE_MODE(1)
#define GI_EDGE_GATE_STARTS		GI_EDGE_GATE_MODE(2)
#define GI_EDGE_GATE_NO_STARTS_OR_STOPS	GI_EDGE_GATE_MODE(3)
#define GI_EDGE_GATE_MODE_MASK		GI_EDGE_GATE_MODE(3)
#define GI_STOP_MODE(x)			(((x) & 0x3) << 5)
#define GI_STOP_ON_GATE			GI_STOP_MODE(0)
#define GI_STOP_ON_GATE_OR_TC		GI_STOP_MODE(1)
#define GI_STOP_ON_GATE_OR_SECOND_TC	GI_STOP_MODE(2)
#define GI_STOP_MODE_MASK		GI_STOP_MODE(3)
#define GI_LOAD_SRC_SEL			BIT(7)
#define GI_OUTPUT_MODE(x)		(((x) & 0x3) << 8)
#define GI_OUTPUT_TC_PULSE		GI_OUTPUT_MODE(1)
#define GI_OUTPUT_TC_TOGGLE		GI_OUTPUT_MODE(2)
#define GI_OUTPUT_TC_OR_GATE_TOGGLE	GI_OUTPUT_MODE(3)
#define GI_OUTPUT_MODE_MASK		GI_OUTPUT_MODE(3)
#define GI_COUNTING_ONCE(x)		(((x) & 0x3) << 10)
#define GI_NO_HARDWARE_DISARM		GI_COUNTING_ONCE(0)
#define GI_DISARM_AT_TC			GI_COUNTING_ONCE(1)
#define GI_DISARM_AT_GATE		GI_COUNTING_ONCE(2)
#define GI_DISARM_AT_TC_OR_GATE		GI_COUNTING_ONCE(3)
#define GI_COUNTING_ONCE_MASK		GI_COUNTING_ONCE(3)
#define GI_LOADING_ON_TC		BIT(12)
#define GI_GATE_POL_INVERT		BIT(13)
#define GI_LOADING_ON_GATE		BIT(14)
#define GI_RELOAD_SRC_SWITCHING		BIT(15)
#define NITIO_LOADA_REG(x)		(NITIO_G0_LOADA + (x))
#define NITIO_LOADB_REG(x)		(NITIO_G0_LOADB + (x))
#define NITIO_INPUT_SEL_REG(x)		(NITIO_G0_INPUT_SEL + (x))
#define GI_READ_ACKS_IRQ		BIT(0)
#define GI_WRITE_ACKS_IRQ		BIT(1)
#define GI_BITS_TO_SRC(x)		(((x) >> 2) & 0x1f)
#define GI_SRC_SEL(x)			(((x) & 0x1f) << 2)
#define GI_SRC_SEL_MASK			GI_SRC_SEL(0x1f)
#define GI_BITS_TO_GATE(x)		(((x) >> 7) & 0x1f)
#define GI_GATE_SEL(x)			(((x) & 0x1f) << 7)
#define GI_GATE_SEL_MASK		GI_GATE_SEL(0x1f)
#define GI_GATE_SEL_LOAD_SRC		BIT(12)
#define GI_OR_GATE			BIT(13)
#define GI_OUTPUT_POL_INVERT		BIT(14)
#define GI_SRC_POL_INVERT		BIT(15)
#define NITIO_CNT_MODE_REG(x)		(NITIO_G0_CNT_MODE + (x))
#define GI_CNT_MODE(x)			(((x) & 0x7) << 0)
#define GI_CNT_MODE_NORMAL		GI_CNT_MODE(0)
#define GI_CNT_MODE_QUADX1		GI_CNT_MODE(1)
#define GI_CNT_MODE_QUADX2		GI_CNT_MODE(2)
#define GI_CNT_MODE_QUADX4		GI_CNT_MODE(3)
#define GI_CNT_MODE_TWO_PULSE		GI_CNT_MODE(4)
#define GI_CNT_MODE_SYNC_SRC		GI_CNT_MODE(6)
#define GI_CNT_MODE_MASK		GI_CNT_MODE(7)
#define GI_INDEX_MODE			BIT(4)
#define GI_INDEX_PHASE(x)		(((x) & 0x3) << 5)
#define GI_INDEX_PHASE_MASK		GI_INDEX_PHASE(3)
#define GI_HW_ARM_ENA			BIT(7)
#define GI_HW_ARM_SEL(x)		((x) << 8)
#define GI_660X_HW_ARM_SEL_MASK		GI_HW_ARM_SEL(0x7)

Annotation

Implementation Notes