drivers/comedi/drivers/z8536.h

Source file repositories/reference/linux-study-clean/drivers/comedi/drivers/z8536.h

File Facts

System
Linux kernel
Corpus path
drivers/comedi/drivers/z8536.h
Extension
.h
Size
8856 bytes
Lines
211
Domain
Driver Families
Bucket
drivers/comedi
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _Z8536_H
#define _Z8536_H

/* Master Interrupt Control register */
#define Z8536_INT_CTRL_REG		0x00
#define Z8536_INT_CTRL_MIE		BIT(7)	/* Master Interrupt Enable */
#define Z8536_INT_CTRL_DLC		BIT(6)	/* Disable Lower Chain */
#define Z8536_INT_CTRL_NV		BIT(5)	/* No Vector */
#define Z8536_INT_CTRL_PA_VIS		BIT(4)	/* Port A Vect Inc Status */
#define Z8536_INT_CTRL_PB_VIS		BIT(3)	/* Port B Vect Inc Status */
#define Z8536_INT_CTRL_VT_VIS		BIT(2)	/* C/T Vect Inc Status */
#define Z8536_INT_CTRL_RJA		BIT(1)	/* Right Justified Addresses */
#define Z8536_INT_CTRL_RESET		BIT(0)	/* Reset */

/* Master Configuration Control register */
#define Z8536_CFG_CTRL_REG		0x01
#define Z8536_CFG_CTRL_PBE		BIT(7)	/* Port B Enable */
#define Z8536_CFG_CTRL_CT1E		BIT(6)	/* C/T 1 Enable */
#define Z8536_CFG_CTRL_CT2E		BIT(5)	/* C/T 2 Enable */
#define Z8536_CFG_CTRL_PCE_CT3E		BIT(4)	/* Port C & C/T 3 Enable */
#define Z8536_CFG_CTRL_PLC		BIT(3)	/* Port A/B Link Control */
#define Z8536_CFG_CTRL_PAE		BIT(2)	/* Port A Enable */
#define Z8536_CFG_CTRL_LC(x)		(((x) & 0x3) << 0)  /* Link Control */
#define Z8536_CFG_CTRL_LC_INDEP		Z8536_CFG_CTRL_LC(0)/* Independent */
#define Z8536_CFG_CTRL_LC_GATE		Z8536_CFG_CTRL_LC(1)/* 1 Gates 2 */
#define Z8536_CFG_CTRL_LC_TRIG		Z8536_CFG_CTRL_LC(2)/* 1 Triggers 2 */
#define Z8536_CFG_CTRL_LC_CLK		Z8536_CFG_CTRL_LC(3)/* 1 Clocks 2 */
#define Z8536_CFG_CTRL_LC_MASK		Z8536_CFG_CTRL_LC(3)

/* Interrupt Vector registers */
#define Z8536_PA_INT_VECT_REG		0x02
#define Z8536_PB_INT_VECT_REG		0x03
#define Z8536_CT_INT_VECT_REG		0x04
#define Z8536_CURR_INT_VECT_REG		0x1f

/* Port A/B & Counter/Timer 1/2/3 Command and Status registers */
#define Z8536_PA_CMDSTAT_REG		0x08
#define Z8536_PB_CMDSTAT_REG		0x09
#define Z8536_CT1_CMDSTAT_REG		0x0a
#define Z8536_CT2_CMDSTAT_REG		0x0b
#define Z8536_CT3_CMDSTAT_REG		0x0c
#define Z8536_CT_CMDSTAT_REG(x)		(0x0a + (x))
#define Z8536_CMD(x)			(((x) & 0x7) << 5)
#define Z8536_CMD_NULL			Z8536_CMD(0)	/* Null Code */
#define Z8536_CMD_CLR_IP_IUS		Z8536_CMD(1)	/* Clear IP & IUS */
#define Z8536_CMD_SET_IUS		Z8536_CMD(2)	/* Set IUS */
#define Z8536_CMD_CLR_IUS		Z8536_CMD(3)	/* Clear IUS */
#define Z8536_CMD_SET_IP		Z8536_CMD(4)	/* Set IP */
#define Z8536_CMD_CLR_IP		Z8536_CMD(5)	/* Clear IP */
#define Z8536_CMD_SET_IE		Z8536_CMD(6)	/* Set IE */
#define Z8536_CMD_CLR_IE		Z8536_CMD(7)	/* Clear IE */
#define Z8536_CMD_MASK			Z8536_CMD(7)

#define Z8536_STAT_IUS			BIT(7)	/* Interrupt Under Service */
#define Z8536_STAT_IE			BIT(6)	/* Interrupt Enable */
#define Z8536_STAT_IP			BIT(5)	/* Interrupt Pending */
#define Z8536_STAT_ERR			BIT(4)	/* Interrupt Error */
#define Z8536_STAT_IE_IP		(Z8536_STAT_IE | Z8536_STAT_IP)

#define Z8536_PAB_STAT_ORE		BIT(3)	/* Output Register Empty */
#define Z8536_PAB_STAT_IRF		BIT(2)	/* Input Register Full */
#define Z8536_PAB_STAT_PMF		BIT(1)	/* Pattern Match Flag */
#define Z8536_PAB_CMDSTAT_IOE		BIT(0)	/* Interrupt On Error */

#define Z8536_CT_CMD_RCC		BIT(3)	/* Read Counter Control */
#define Z8536_CT_CMDSTAT_GCB		BIT(2)	/* Gate Command Bit */
#define Z8536_CT_CMD_TCB		BIT(1)	/* Trigger Command Bit */
#define Z8536_CT_STAT_CIP		BIT(0)	/* Count In Progress */

/* Port Data registers */
#define Z8536_PA_DATA_REG		0x0d
#define Z8536_PB_DATA_REG		0x0e
#define Z8536_PC_DATA_REG		0x0f

/* Counter/Timer 1/2/3 Current Count registers */
#define Z8536_CT1_VAL_MSB_REG		0x10
#define Z8536_CT1_VAL_LSB_REG		0x11
#define Z8536_CT2_VAL_MSB_REG		0x12
#define Z8536_CT2_VAL_LSB_REG		0x13
#define Z8536_CT3_VAL_MSB_REG		0x14
#define Z8536_CT3_VAL_LSB_REG		0x15
#define Z8536_CT_VAL_MSB_REG(x)		(0x10 + ((x) * 2))
#define Z8536_CT_VAL_LSB_REG(x)		(0x11 + ((x) * 2))

/* Counter/Timer 1/2/3 Time Constant registers */
#define Z8536_CT1_RELOAD_MSB_REG	0x16
#define Z8536_CT1_RELOAD_LSB_REG	0x17
#define Z8536_CT2_RELOAD_MSB_REG	0x18
#define Z8536_CT2_RELOAD_LSB_REG	0x19
#define Z8536_CT3_RELOAD_MSB_REG	0x1a

Annotation

Implementation Notes