drivers/cpufreq/sa1110-cpufreq.c
Source file repositories/reference/linux-study-clean/drivers/cpufreq/sa1110-cpufreq.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/cpufreq/sa1110-cpufreq.c- Extension
.c- Size
- 8859 bytes
- Lines
- 368
- Domain
- Driver Families
- Bucket
- drivers/cpufreq
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/cpufreq.hlinux/delay.hlinux/init.hlinux/io.hlinux/kernel.hlinux/moduleparam.hlinux/types.hasm/cputype.hasm/mach-types.hmach/generic.hmach/hardware.h
Detected Declarations
struct sdram_paramsstruct sdram_infofunction ns_to_cyclesfunction set_mdcasfunction sdram_calculate_timingfunction sdram_set_refreshfunction clockfunction sa1110_targetfunction sa1110_cpu_initfunction sa1110_clk_init
Annotated Snippet
struct sdram_params {
const char name[20];
u_char rows; /* bits */
u_char cas_latency; /* cycles */
u_char tck; /* clock cycle time (ns) */
u_char trcd; /* activate to r/w (ns) */
u_char trp; /* precharge to activate (ns) */
u_char twr; /* write recovery time (ns) */
u_short refresh; /* refresh time for array (us) */
};
struct sdram_info {
u_int mdcnfg;
u_int mdrefr;
u_int mdcas[3];
};
static struct sdram_params sdram_tbl[] __initdata = {
{ /* Toshiba TC59SM716 CL2 */
.name = "TC59SM716-CL2",
.rows = 12,
.tck = 10,
.trcd = 20,
.trp = 20,
.twr = 10,
.refresh = 64000,
.cas_latency = 2,
}, { /* Toshiba TC59SM716 CL3 */
.name = "TC59SM716-CL3",
.rows = 12,
.tck = 8,
.trcd = 20,
.trp = 20,
.twr = 8,
.refresh = 64000,
.cas_latency = 3,
}, { /* Samsung K4S641632D TC75 */
.name = "K4S641632D",
.rows = 14,
.tck = 9,
.trcd = 27,
.trp = 20,
.twr = 9,
.refresh = 64000,
.cas_latency = 3,
}, { /* Samsung K4S281632B-1H */
.name = "K4S281632B-1H",
.rows = 12,
.tck = 10,
.trp = 20,
.twr = 10,
.refresh = 64000,
.cas_latency = 3,
}, { /* Samsung KM416S4030CT */
.name = "KM416S4030CT",
.rows = 13,
.tck = 8,
.trcd = 24, /* 3 CLKs */
.trp = 24, /* 3 CLKs */
.twr = 16, /* Trdl: 2 CLKs */
.refresh = 64000,
.cas_latency = 3,
}, { /* Winbond W982516AH75L CL3 */
.name = "W982516AH75L",
.rows = 16,
.tck = 8,
.trcd = 20,
.trp = 20,
.twr = 8,
.refresh = 64000,
.cas_latency = 3,
}, { /* Micron MT48LC8M16A2TG-75 */
.name = "MT48LC8M16A2TG-75",
.rows = 12,
.tck = 8,
.trcd = 20,
.trp = 20,
.twr = 8,
.refresh = 64000,
.cas_latency = 3,
},
};
static struct sdram_params sdram_params;
/*
* Given a period in ns and frequency in khz, calculate the number of
* cycles of frequency in period. Note that we round up to the next
* cycle, even if we are only slightly over.
*/
Annotation
- Immediate include surface: `linux/cpufreq.h`, `linux/delay.h`, `linux/init.h`, `linux/io.h`, `linux/kernel.h`, `linux/moduleparam.h`, `linux/types.h`, `asm/cputype.h`.
- Detected declarations: `struct sdram_params`, `struct sdram_info`, `function ns_to_cycles`, `function set_mdcas`, `function sdram_calculate_timing`, `function sdram_set_refresh`, `function clock`, `function sa1110_target`, `function sa1110_cpu_init`, `function sa1110_clk_init`.
- Atlas domain: Driver Families / drivers/cpufreq.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.