drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
Source file repositories/reference/linux-study-clean/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c- Extension
.c- Size
- 30859 bytes
- Lines
- 1141
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
crypto/engine.hcrypto/internal/hash.hcrypto/internal/rng.hcrypto/internal/skcipher.hlinux/clk.hlinux/delay.hlinux/dma-mapping.hlinux/err.hlinux/interrupt.hlinux/io.hlinux/irq.hlinux/kernel.hlinux/module.hlinux/of.hlinux/platform_device.hlinux/pm_runtime.hlinux/reset.hsun8i-ce.h
Detected Declarations
function sun8i_ce_dump_task_descriptorsfunction sun8i_ce_get_engine_numberfunction sun8i_ce_run_taskfunction ce_irq_handlerfunction sun8i_ce_debugfs_showfunction sun8i_ce_free_chanlistfunction sun8i_ce_allocate_chanlistfunction sun8i_ce_pm_suspendfunction sun8i_ce_pm_resumefunction sun8i_ce_pm_initfunction sun8i_ce_get_clksfunction sun8i_ce_register_algsfunction sun8i_ce_unregister_algsfunction sun8i_ce_probefunction sun8i_ce_remove
Annotated Snippet
if (v) {
dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
sun8i_ce_dump_task_descriptors(&ce->chanlist[flow]);
err = -EFAULT;
}
if (v & CE_ERR_ALGO_NOTSUP)
dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
if (v & CE_ERR_DATALEN)
dev_err(ce->dev, "CE ERROR: data length error\n");
if (v & CE_ERR_KEYSRAM)
dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
break;
case ESR_A64:
case ESR_D1:
case ESR_H5:
case ESR_R40:
v >>= (flow * 4);
v &= 0xF;
if (v) {
dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
sun8i_ce_dump_task_descriptors(&ce->chanlist[flow]);
err = -EFAULT;
}
if (v & CE_ERR_ALGO_NOTSUP)
dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
if (v & CE_ERR_DATALEN)
dev_err(ce->dev, "CE ERROR: data length error\n");
if (v & CE_ERR_KEYSRAM)
dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
break;
case ESR_H6:
v >>= (flow * 8);
v &= 0xFF;
if (v) {
dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
sun8i_ce_dump_task_descriptors(&ce->chanlist[flow]);
err = -EFAULT;
}
if (v & CE_ERR_ALGO_NOTSUP)
dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
if (v & CE_ERR_DATALEN)
dev_err(ce->dev, "CE ERROR: data length error\n");
if (v & CE_ERR_KEYSRAM)
dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
if (v & CE_ERR_ADDR_INVALID)
dev_err(ce->dev, "CE ERROR: address invalid\n");
if (v & CE_ERR_KEYLADDER)
dev_err(ce->dev, "CE ERROR: key ladder configuration error\n");
break;
}
return err;
}
static irqreturn_t ce_irq_handler(int irq, void *data)
{
struct sun8i_ce_dev *ce = (struct sun8i_ce_dev *)data;
int flow = 0;
u32 p;
p = readl(ce->base + CE_ISR);
for (flow = 0; flow < MAXFLOW; flow++) {
if (p & (BIT(flow))) {
writel(BIT(flow), ce->base + CE_ISR);
ce->chanlist[flow].status = 1;
complete(&ce->chanlist[flow].complete);
}
}
return IRQ_HANDLED;
}
static struct sun8i_ce_alg_template ce_algs[] = {
{
.type = CRYPTO_ALG_TYPE_SKCIPHER,
.ce_algo_id = CE_ID_CIPHER_AES,
.ce_blockmode = CE_ID_OP_CBC,
.alg.skcipher.base = {
.base = {
.cra_name = "cbc(aes)",
.cra_driver_name = "cbc-aes-sun8i-ce",
.cra_priority = 400,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
CRYPTO_ALG_ASYNC |
CRYPTO_ALG_NEED_FALLBACK,
.cra_ctxsize = sizeof(struct sun8i_cipher_tfm_ctx),
.cra_module = THIS_MODULE,
.cra_alignmask = 0xf,
.cra_init = sun8i_ce_cipher_init,
Annotation
- Immediate include surface: `crypto/engine.h`, `crypto/internal/hash.h`, `crypto/internal/rng.h`, `crypto/internal/skcipher.h`, `linux/clk.h`, `linux/delay.h`, `linux/dma-mapping.h`, `linux/err.h`.
- Detected declarations: `function sun8i_ce_dump_task_descriptors`, `function sun8i_ce_get_engine_number`, `function sun8i_ce_run_task`, `function ce_irq_handler`, `function sun8i_ce_debugfs_show`, `function sun8i_ce_free_chanlist`, `function sun8i_ce_allocate_chanlist`, `function sun8i_ce_pm_suspend`, `function sun8i_ce_pm_resume`, `function sun8i_ce_pm_init`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.