drivers/crypto/aspeed/aspeed-hace-crypto.c
Source file repositories/reference/linux-study-clean/drivers/crypto/aspeed/aspeed-hace-crypto.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/aspeed/aspeed-hace-crypto.c- Extension
.c- Size
- 26297 bytes
- Lines
- 956
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
aspeed-hace.hcrypto/des.hcrypto/engine.hcrypto/internal/des.hcrypto/internal/skcipher.hlinux/dma-mapping.hlinux/err.hlinux/io.hlinux/kernel.hlinux/module.hlinux/scatterlist.hlinux/string.h
Detected Declarations
function Copyrightfunction aspeed_crypto_need_fallbackfunction aspeed_hace_crypto_handle_queuefunction aspeed_crypto_do_requestfunction aspeed_sk_completefunction aspeed_sk_transfer_sgfunction aspeed_sk_transferfunction aspeed_sk_startfunction aspeed_sk_start_sgfunction for_each_sgfunction for_each_sgfunction aspeed_hace_skcipher_triggerfunction aspeed_des_cryptfunction aspeed_des_setkeyfunction aspeed_tdes_ctr_decryptfunction aspeed_tdes_ctr_encryptfunction aspeed_tdes_cbc_decryptfunction aspeed_tdes_cbc_encryptfunction aspeed_tdes_ecb_decryptfunction aspeed_tdes_ecb_encryptfunction aspeed_des_ctr_decryptfunction aspeed_des_ctr_encryptfunction aspeed_des_cbc_decryptfunction aspeed_des_cbc_encryptfunction aspeed_des_ecb_decryptfunction aspeed_des_ecb_encryptfunction aspeed_aes_cryptfunction aspeed_aes_setkeyfunction aspeed_aes_ctr_decryptfunction aspeed_aes_ctr_encryptfunction aspeed_aes_cbc_decryptfunction aspeed_aes_cbc_encryptfunction aspeed_aes_ecb_decryptfunction aspeed_aes_ecb_encryptfunction aspeed_crypto_cra_initfunction aspeed_crypto_cra_exitfunction aspeed_unregister_hace_crypto_algsfunction aspeed_register_hace_crypto_algs
Annotated Snippet
aspeed_crypto_need_fallback(req)) {
CIPHER_DBG(hace_dev, "SW fallback\n");
return aspeed_crypto_do_fallback(req);
}
return crypto_transfer_skcipher_request_to_engine(
hace_dev->crypt_engine_crypto, req);
}
static int aspeed_crypto_do_request(struct crypto_engine *engine, void *areq)
{
struct skcipher_request *req = skcipher_request_cast(areq);
struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req);
struct aspeed_cipher_ctx *ctx = crypto_skcipher_ctx(cipher);
struct aspeed_hace_dev *hace_dev = ctx->hace_dev;
struct aspeed_engine_crypto *crypto_engine;
int rc;
crypto_engine = &hace_dev->crypto_engine;
crypto_engine->req = req;
crypto_engine->flags |= CRYPTO_FLAGS_BUSY;
rc = ctx->start(hace_dev);
if (rc != -EINPROGRESS)
return -EIO;
return 0;
}
static int aspeed_sk_complete(struct aspeed_hace_dev *hace_dev, int err)
{
struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
struct aspeed_cipher_reqctx *rctx;
struct skcipher_request *req;
CIPHER_DBG(hace_dev, "\n");
req = crypto_engine->req;
rctx = skcipher_request_ctx(req);
if (rctx->enc_cmd & HACE_CMD_IV_REQUIRE) {
if (rctx->enc_cmd & HACE_CMD_DES_SELECT)
memcpy(req->iv, crypto_engine->cipher_ctx +
DES_KEY_SIZE, DES_KEY_SIZE);
else
memcpy(req->iv, crypto_engine->cipher_ctx,
AES_BLOCK_SIZE);
}
crypto_engine->flags &= ~CRYPTO_FLAGS_BUSY;
crypto_finalize_skcipher_request(hace_dev->crypt_engine_crypto, req,
err);
return err;
}
static int aspeed_sk_transfer_sg(struct aspeed_hace_dev *hace_dev)
{
struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
struct device *dev = hace_dev->dev;
struct aspeed_cipher_reqctx *rctx;
struct skcipher_request *req;
CIPHER_DBG(hace_dev, "\n");
req = crypto_engine->req;
rctx = skcipher_request_ctx(req);
if (req->src == req->dst) {
dma_unmap_sg(dev, req->src, rctx->src_nents, DMA_BIDIRECTIONAL);
} else {
dma_unmap_sg(dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
dma_unmap_sg(dev, req->dst, rctx->dst_nents, DMA_FROM_DEVICE);
}
return aspeed_sk_complete(hace_dev, 0);
}
static int aspeed_sk_transfer(struct aspeed_hace_dev *hace_dev)
{
struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
struct aspeed_cipher_reqctx *rctx;
struct skcipher_request *req;
struct scatterlist *out_sg;
int nbytes = 0;
int rc = 0;
req = crypto_engine->req;
Annotation
- Immediate include surface: `aspeed-hace.h`, `crypto/des.h`, `crypto/engine.h`, `crypto/internal/des.h`, `crypto/internal/skcipher.h`, `linux/dma-mapping.h`, `linux/err.h`, `linux/io.h`.
- Detected declarations: `function Copyright`, `function aspeed_crypto_need_fallback`, `function aspeed_hace_crypto_handle_queue`, `function aspeed_crypto_do_request`, `function aspeed_sk_complete`, `function aspeed_sk_transfer_sg`, `function aspeed_sk_transfer`, `function aspeed_sk_start`, `function aspeed_sk_start_sg`, `function for_each_sg`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.