drivers/crypto/aspeed/aspeed-hace.h
Source file repositories/reference/linux-study-clean/drivers/crypto/aspeed/aspeed-hace.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/aspeed/aspeed-hace.h- Extension
.h- Size
- 7697 bytes
- Lines
- 275
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
crypto/aes.hcrypto/engine.hcrypto/hash.hcrypto/sha2.hlinux/bits.hlinux/compiler_attributes.hlinux/interrupt.hlinux/types.h
Detected Declarations
struct aspeed_hace_devstruct scatterliststruct aspeed_sg_liststruct aspeed_engine_hashstruct aspeed_sham_ctxstruct aspeed_sham_reqctxstruct aspeed_engine_cryptostruct aspeed_cipher_ctxstruct aspeed_cipher_reqctxstruct aspeed_hace_devstruct aspeed_hace_algenum aspeed_version
Annotated Snippet
struct aspeed_sg_list {
__le32 len;
__le32 phy_addr;
};
struct aspeed_engine_hash {
struct tasklet_struct done_task;
unsigned long flags;
struct ahash_request *req;
/* input buffer */
void *ahash_src_addr;
dma_addr_t ahash_src_dma_addr;
dma_addr_t src_dma;
dma_addr_t digest_dma;
size_t src_length;
/* callback func */
aspeed_hace_fn_t resume;
aspeed_hace_fn_t dma_prepare;
};
struct aspeed_sham_ctx {
struct aspeed_hace_dev *hace_dev;
};
struct aspeed_sham_reqctx {
/* DMA buffer written by hardware */
u8 digest[SHA512_DIGEST_SIZE] __aligned(64);
/* Software state sorted by size. */
u64 digcnt[2];
unsigned long flags; /* final update flag should no use*/
u32 cmd; /* trigger cmd */
/* walk state */
struct scatterlist *src_sg;
int src_nents;
unsigned int offset; /* offset in current sg */
unsigned int total; /* per update length */
size_t digsize;
size_t block_size;
size_t ivsize;
dma_addr_t buffer_dma_addr;
dma_addr_t digest_dma_addr;
/* This is DMA too but read-only for hardware. */
u8 buffer[SHA512_BLOCK_SIZE + 16];
};
struct aspeed_engine_crypto {
struct tasklet_struct done_task;
unsigned long flags;
struct skcipher_request *req;
/* context buffer */
void *cipher_ctx;
dma_addr_t cipher_ctx_dma;
/* input buffer, could be single/scatter-gather lists */
void *cipher_addr;
dma_addr_t cipher_dma_addr;
/* output buffer, only used in scatter-gather lists */
void *dst_sg_addr;
dma_addr_t dst_sg_dma_addr;
/* callback func */
aspeed_hace_fn_t resume;
};
struct aspeed_cipher_ctx {
struct aspeed_hace_dev *hace_dev;
int key_len;
u8 key[AES_MAX_KEYLENGTH];
/* callback func */
aspeed_hace_fn_t start;
struct crypto_skcipher *fallback_tfm;
};
struct aspeed_cipher_reqctx {
int enc_cmd;
int src_nents;
Annotation
- Immediate include surface: `crypto/aes.h`, `crypto/engine.h`, `crypto/hash.h`, `crypto/sha2.h`, `linux/bits.h`, `linux/compiler_attributes.h`, `linux/interrupt.h`, `linux/types.h`.
- Detected declarations: `struct aspeed_hace_dev`, `struct scatterlist`, `struct aspeed_sg_list`, `struct aspeed_engine_hash`, `struct aspeed_sham_ctx`, `struct aspeed_sham_reqctx`, `struct aspeed_engine_crypto`, `struct aspeed_cipher_ctx`, `struct aspeed_cipher_reqctx`, `struct aspeed_hace_dev`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.