drivers/crypto/axis/artpec6_crypto.c
Source file repositories/reference/linux-study-clean/drivers/crypto/axis/artpec6_crypto.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/axis/artpec6_crypto.c- Extension
.c- Size
- 79385 bytes
- Lines
- 2981
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/crypto.hlinux/debugfs.hlinux/delay.hlinux/dma-mapping.hlinux/fault-inject.hlinux/init.hlinux/interrupt.hlinux/kernel.hlinux/list.hlinux/module.hlinux/of.hlinux/platform_device.hlinux/scatterlist.hlinux/slab.hcrypto/aes.hcrypto/gcm.hcrypto/internal/aead.hcrypto/internal/hash.hcrypto/internal/skcipher.hcrypto/scatterwalk.hcrypto/sha1.hcrypto/sha2.hcrypto/xts.h
Detected Declarations
struct pdma_descr_ctrlstruct pdma_data_descrstruct pdma_short_descrstruct pdma_descrstruct pdma_stat_descrstruct artpec6_crypto_bounce_bufferstruct artpec6_crypto_dma_mapstruct artpec6_crypto_dma_descriptorsstruct artpec6_cryptostruct artpec6_crypto_req_commonstruct artpec6_hash_request_contextstruct artpec6_hash_export_statestruct artpec6_hashalg_contextstruct artpec6_crypto_request_contextstruct artpec6_cryptotfm_contextstruct artpec6_crypto_aead_hw_ctxstruct artpec6_crypto_aead_req_ctxstruct artpec6_crypto_walkenum artpec6_crypto_variantenum artpec6_crypto_hash_flagsfunction artpec6_crypto_walk_initfunction artpec6_crypto_walk_advancefunction artpec6_crypto_walk_chunklenfunction artpec6_crypto_walk_chunk_physfunction artpec6_crypto_copy_bounce_buffersfunction list_for_each_entry_safefunction artpec6_crypto_busyfunction artpec6_crypto_submitfunction artpec6_crypto_start_dmafunction artpec6_crypto_init_dma_operationfunction fault_inject_dma_descrfunction artpec6_crypto_setup_out_descr_physfunction artpec6_crypto_setup_out_descr_shortfunction artpec6_crypto_dma_map_pagefunction artpec6_crypto_dma_map_singlefunction artpec6_crypto_dma_map_descsfunction artpec6_crypto_dma_unmap_allfunction artpec6_crypto_setup_out_descr_shortfunction artpec6_crypto_setup_in_descr_physfunction artpec6_crypto_setup_in_descrfunction artpec6_crypto_alloc_bouncefunction setup_bounce_buffer_infunction artpec6_crypto_setup_sg_descrs_infunction artpec6_crypto_setup_sg_descrs_outfunction artpec6_crypto_terminate_out_descrsfunction artpec6_crypto_terminate_out_descrsfunction create_hash_padfunction artpec6_crypto_common_init
Annotated Snippet
struct pdma_descr_ctrl {
unsigned char short_descr : 1;
unsigned char pad1 : 1;
unsigned char eop : 1;
unsigned char intr : 1;
unsigned char short_len : 3;
unsigned char pad2 : 1;
} __packed;
struct pdma_data_descr {
unsigned int len : 24;
unsigned int buf : 32;
} __packed;
struct pdma_short_descr {
unsigned char data[7];
} __packed;
struct pdma_descr {
struct pdma_descr_ctrl ctrl;
union {
struct pdma_data_descr data;
struct pdma_short_descr shrt;
};
};
struct pdma_stat_descr {
unsigned char pad1 : 1;
unsigned char pad2 : 1;
unsigned char eop : 1;
unsigned char pad3 : 5;
unsigned int len : 24;
};
/* Each descriptor array can hold max 64 entries */
#define PDMA_DESCR_COUNT 64
#define MODULE_NAME "Artpec-6 CA"
/* Hash modes (including HMAC variants) */
#define ARTPEC6_CRYPTO_HASH_SHA1 1
#define ARTPEC6_CRYPTO_HASH_SHA256 2
/* Crypto modes */
#define ARTPEC6_CRYPTO_CIPHER_AES_ECB 1
#define ARTPEC6_CRYPTO_CIPHER_AES_CBC 2
#define ARTPEC6_CRYPTO_CIPHER_AES_CTR 3
#define ARTPEC6_CRYPTO_CIPHER_AES_XTS 5
/* The PDMA is a DMA-engine tightly coupled with a ciphering engine.
* It operates on a descriptor array with up to 64 descriptor entries.
* The arrays must be 64 byte aligned in memory.
*
* The ciphering unit has no registers and is completely controlled by
* a 4-byte metadata that is inserted at the beginning of each dma packet.
*
* A dma packet is a sequence of descriptors terminated by setting the .eop
* field in the final descriptor of the packet.
*
* Multiple packets are used for providing context data, key data and
* the plain/ciphertext.
*
* PDMA Descriptors (Array)
* +------+------+------+~~+-------+------+----
* | 0 | 1 | 2 |~~| 11 EOP| 12 | ....
* +--+---+--+---+----+-+~~+-------+----+-+----
* | | | | |
* | | | | |
* __|__ +-------++-------++-------+ +----+
* | MD | |Payload||Payload||Payload| | MD |
* +-----+ +-------++-------++-------+ +----+
*/
struct artpec6_crypto_bounce_buffer {
struct list_head list;
size_t length;
struct scatterlist *sg;
size_t offset;
/* buf is aligned to ARTPEC_CACHE_LINE_MAX and
* holds up to ARTPEC_CACHE_LINE_MAX bytes data.
*/
void *buf;
};
struct artpec6_crypto_dma_map {
dma_addr_t dma_addr;
size_t size;
enum dma_data_direction dir;
};
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/crypto.h`, `linux/debugfs.h`, `linux/delay.h`, `linux/dma-mapping.h`, `linux/fault-inject.h`, `linux/init.h`, `linux/interrupt.h`.
- Detected declarations: `struct pdma_descr_ctrl`, `struct pdma_data_descr`, `struct pdma_short_descr`, `struct pdma_descr`, `struct pdma_stat_descr`, `struct artpec6_crypto_bounce_buffer`, `struct artpec6_crypto_dma_map`, `struct artpec6_crypto_dma_descriptors`, `struct artpec6_crypto`, `struct artpec6_crypto_req_common`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.