drivers/crypto/bcm/spum.h
Source file repositories/reference/linux-study-clean/drivers/crypto/bcm/spum.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/bcm/spum.h- Extension
.h- Size
- 4914 bytes
- Lines
- 164
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct BDESC_HEADERstruct BD_HEADERstruct MHEADERstruct SCTXstruct SPUHEADER
Annotated Snippet
struct BDESC_HEADER {
__be16 offset_mac; /* word 0 [31-16] */
__be16 length_mac; /* word 0 [15-0] */
__be16 offset_crypto; /* word 1 [31-16] */
__be16 length_crypto; /* word 1 [15-0] */
__be16 offset_icv; /* word 2 [31-16] */
__be16 offset_iv; /* word 2 [15-0] */
};
/* Buffer Data Header [BD]. SPU in big-endian mode. */
struct BD_HEADER {
__be16 size;
__be16 prev_length;
};
/* Command Context Header. SPU-M in big endian mode. */
struct MHEADER {
u8 flags; /* [31:24] */
u8 op_code; /* [23:16] */
u16 reserved; /* [15:0] */
};
/* MH header flags bits */
#define MH_SUPDT_PRES BIT(0)
#define MH_HASH_PRES BIT(2)
#define MH_BD_PRES BIT(3)
#define MH_MFM_PRES BIT(4)
#define MH_BDESC_PRES BIT(5)
#define MH_SCTX_PRES BIT(7)
/* SCTX word 0 bit offsets and fields masks */
#define SCTX_SIZE 0x000000FF
/* SCTX word 1 bit shifts and field masks */
#define UPDT_OFST 0x000000FF /* offset of SCTX updateable fld */
#define HASH_TYPE 0x00000300 /* hash alg operation type */
#define HASH_TYPE_SHIFT 8
#define HASH_MODE 0x00001C00 /* one of spu2_hash_mode */
#define HASH_MODE_SHIFT 10
#define HASH_ALG 0x0000E000 /* hash algorithm */
#define HASH_ALG_SHIFT 13
#define CIPHER_TYPE 0x00030000 /* encryption operation type */
#define CIPHER_TYPE_SHIFT 16
#define CIPHER_MODE 0x001C0000 /* encryption mode */
#define CIPHER_MODE_SHIFT 18
#define CIPHER_ALG 0x00E00000 /* encryption algo */
#define CIPHER_ALG_SHIFT 21
#define ICV_IS_512 BIT(27)
#define ICV_IS_512_SHIFT 27
#define CIPHER_ORDER BIT(30)
#define CIPHER_ORDER_SHIFT 30
#define CIPHER_INBOUND BIT(31)
#define CIPHER_INBOUND_SHIFT 31
/* SCTX word 2 bit shifts and field masks */
#define EXP_IV_SIZE 0x7
#define IV_OFFSET BIT(3)
#define IV_OFFSET_SHIFT 3
#define GEN_IV BIT(5)
#define GEN_IV_SHIFT 5
#define EXPLICIT_IV BIT(6)
#define EXPLICIT_IV_SHIFT 6
#define SCTX_IV BIT(7)
#define SCTX_IV_SHIFT 7
#define ICV_SIZE 0x0F00
#define ICV_SIZE_SHIFT 8
#define CHECK_ICV BIT(12)
#define CHECK_ICV_SHIFT 12
#define INSERT_ICV BIT(13)
#define INSERT_ICV_SHIFT 13
#define BD_SUPPRESS BIT(19)
#define BD_SUPPRESS_SHIFT 19
/* Generic Mode Security Context Structure [SCTX] */
struct SCTX {
/* word 0: protocol flags */
__be32 proto_flags;
/* word 1: cipher flags */
__be32 cipher_flags;
/* word 2: Extended cipher flags */
__be32 ecf;
};
struct SPUHEADER {
struct MHEADER mh;
u32 emh;
struct SCTX sa;
Annotation
- Detected declarations: `struct BDESC_HEADER`, `struct BD_HEADER`, `struct MHEADER`, `struct SCTX`, `struct SPUHEADER`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.