drivers/crypto/cavium/nitrox/nitrox_csr.h

Source file repositories/reference/linux-study-clean/drivers/crypto/cavium/nitrox/nitrox_csr.h

File Facts

System
Linux kernel
Corpus path
drivers/crypto/cavium/nitrox/nitrox_csr.h
Extension
.h
Size
39744 bytes
Lines
1440
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __NITROX_CSR_H
#define __NITROX_CSR_H

#include <asm/byteorder.h>
#include <linux/types.h>

/* EMU clusters */
#define NR_CLUSTERS		4
/* Maximum cores per cluster,
 * varies based on partname
 */
#define AE_CORES_PER_CLUSTER	20
#define SE_CORES_PER_CLUSTER	16

#define AE_MAX_CORES	(AE_CORES_PER_CLUSTER * NR_CLUSTERS)
#define SE_MAX_CORES	(SE_CORES_PER_CLUSTER * NR_CLUSTERS)
#define ZIP_MAX_CORES	5

/* BIST registers */
#define EMU_BIST_STATUSX(_i)	(0x1402700 + ((_i) * 0x40000))
#define UCD_BIST_STATUS		0x12C0070
#define NPS_CORE_BIST_REG	0x10000E8
#define NPS_CORE_NPC_BIST_REG	0x1000128
#define NPS_PKT_SLC_BIST_REG	0x1040088
#define NPS_PKT_IN_BIST_REG	0x1040100
#define POM_BIST_REG		0x11C0100
#define BMI_BIST_REG		0x1140080
#define EFL_CORE_BIST_REGX(_i)	(0x1240100 + ((_i) * 0x400))
#define EFL_TOP_BIST_STAT	0x1241090
#define BMO_BIST_REG		0x1180080
#define LBC_BIST_STATUS		0x1200020
#define PEM_BIST_STATUSX(_i)	(0x1080468 | ((_i) << 18))

/* EMU registers */
#define EMU_SE_ENABLEX(_i)	(0x1400000 + ((_i) * 0x40000))
#define EMU_AE_ENABLEX(_i)	(0x1400008 + ((_i) * 0x40000))
#define EMU_WD_INT_ENA_W1SX(_i)	(0x1402318 + ((_i) * 0x40000))
#define EMU_GE_INT_ENA_W1SX(_i)	(0x1402518 + ((_i) * 0x40000))
#define EMU_FUSE_MAPX(_i)	(0x1402708 + ((_i) * 0x40000))

/* UCD registers */
#define UCD_SE_EID_UCODE_BLOCK_NUMX(_i)	(0x12C0000 + ((_i) * 0x1000))
#define UCD_AE_EID_UCODE_BLOCK_NUMX(_i)	(0x12C0008 + ((_i) * 0x800))
#define UCD_UCODE_LOAD_BLOCK_NUM	0x12C0010
#define UCD_UCODE_LOAD_IDX_DATAX(_i)	(0x12C0018 + ((_i) * 0x20))
#define UCD_SE_CNTX(_i)			(0x12C0040 + ((_i) * 0x1000))
#define UCD_AE_CNTX(_i)			(0x12C0048 + ((_i) * 0x800))

/* AQM registers */
#define AQM_CTL                         0x1300000
#define AQM_INT                         0x1300008
#define AQM_DBELL_OVF_LO                0x1300010
#define AQM_DBELL_OVF_HI                0x1300018
#define AQM_DBELL_OVF_LO_W1S            0x1300020
#define AQM_DBELL_OVF_LO_ENA_W1C        0x1300028
#define AQM_DBELL_OVF_LO_ENA_W1S        0x1300030
#define AQM_DBELL_OVF_HI_W1S            0x1300038
#define AQM_DBELL_OVF_HI_ENA_W1C        0x1300040
#define AQM_DBELL_OVF_HI_ENA_W1S        0x1300048
#define AQM_DMA_RD_ERR_LO               0x1300050
#define AQM_DMA_RD_ERR_HI               0x1300058
#define AQM_DMA_RD_ERR_LO_W1S           0x1300060
#define AQM_DMA_RD_ERR_LO_ENA_W1C       0x1300068
#define AQM_DMA_RD_ERR_LO_ENA_W1S       0x1300070
#define AQM_DMA_RD_ERR_HI_W1S           0x1300078
#define AQM_DMA_RD_ERR_HI_ENA_W1C       0x1300080
#define AQM_DMA_RD_ERR_HI_ENA_W1S       0x1300088
#define AQM_EXEC_NA_LO                  0x1300090
#define AQM_EXEC_NA_HI                  0x1300098
#define AQM_EXEC_NA_LO_W1S              0x13000A0
#define AQM_EXEC_NA_LO_ENA_W1C          0x13000A8
#define AQM_EXEC_NA_LO_ENA_W1S          0x13000B0
#define AQM_EXEC_NA_HI_W1S              0x13000B8
#define AQM_EXEC_NA_HI_ENA_W1C          0x13000C0
#define AQM_EXEC_NA_HI_ENA_W1S          0x13000C8
#define AQM_EXEC_ERR_LO                 0x13000D0
#define AQM_EXEC_ERR_HI                 0x13000D8
#define AQM_EXEC_ERR_LO_W1S             0x13000E0
#define AQM_EXEC_ERR_LO_ENA_W1C         0x13000E8
#define AQM_EXEC_ERR_LO_ENA_W1S         0x13000F0
#define AQM_EXEC_ERR_HI_W1S             0x13000F8
#define AQM_EXEC_ERR_HI_ENA_W1C         0x1300100
#define AQM_EXEC_ERR_HI_ENA_W1S         0x1300108
#define AQM_ECC_INT                     0x1300110
#define AQM_ECC_INT_W1S                 0x1300118
#define AQM_ECC_INT_ENA_W1C             0x1300120
#define AQM_ECC_INT_ENA_W1S             0x1300128
#define AQM_ECC_CTL                     0x1300130
#define AQM_BIST_STATUS                 0x1300138
#define AQM_CMD_INF_THRX(x)             (0x1300400 + ((x) * 0x8))

Annotation

Implementation Notes