drivers/crypto/cavium/nitrox/nitrox_dev.h
Source file repositories/reference/linux-study-clean/drivers/crypto/cavium/nitrox/nitrox_dev.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/cavium/nitrox/nitrox_dev.h- Extension
.h- Size
- 6525 bytes
- Lines
- 303
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/dma-mapping.hlinux/interrupt.hlinux/pci.hlinux/if.h
Detected Declarations
struct nitrox_cmdqstruct nitrox_hwstruct nitrox_statsstruct nitrox_q_vectorstruct nitrox_vfdevstruct nitrox_iovstruct nitrox_deviceenum mcode_typeenum ndev_stateenum vf_modefunction nitrox_read_csrfunction nitrox_write_csrfunction nitrox_readyfunction nitrox_vfdev_ready
Annotated Snippet
struct nitrox_cmdq {
spinlock_t cmd_qlock;
spinlock_t resp_qlock;
spinlock_t backlog_qlock;
struct nitrox_device *ndev;
struct list_head response_head;
struct list_head backlog_head;
u8 __iomem *dbell_csr_addr;
u8 __iomem *compl_cnt_csr_addr;
u8 *base;
dma_addr_t dma;
struct work_struct backlog_qflush;
atomic_t pending_count;
atomic_t backlog_count;
int write_idx;
u8 instr_size;
u8 qno;
u32 qsize;
u8 *unalign_base;
dma_addr_t unalign_dma;
};
/**
* struct nitrox_hw - NITROX hardware information
* @partname: partname ex: CNN55xxx-xxx
* @fw_name: firmware version
* @freq: NITROX frequency
* @vendor_id: vendor ID
* @device_id: device ID
* @revision_id: revision ID
* @se_cores: number of symmetric cores
* @ae_cores: number of asymmetric cores
* @zip_cores: number of zip cores
*/
struct nitrox_hw {
char partname[IFNAMSIZ * 2];
char fw_name[CNN55XX_MAX_UCD_BLOCKS][VERSION_LEN];
int freq;
u16 vendor_id;
u16 device_id;
u8 revision_id;
u8 se_cores;
u8 ae_cores;
u8 zip_cores;
};
struct nitrox_stats {
atomic64_t posted;
atomic64_t completed;
atomic64_t dropped;
};
#define IRQ_NAMESZ 32
struct nitrox_q_vector {
char name[IRQ_NAMESZ];
bool valid;
int ring;
struct tasklet_struct resp_tasklet;
union {
struct nitrox_cmdq *cmdq;
struct nitrox_device *ndev;
};
};
enum mcode_type {
MCODE_TYPE_INVALID,
MCODE_TYPE_AE,
MCODE_TYPE_SE_SSL,
MCODE_TYPE_SE_IPSEC,
};
/**
* mbox_msg - Mailbox message data
* @type: message type
* @opcode: message opcode
* @data: message data
*/
union mbox_msg {
u64 value;
struct {
u64 type: 2;
Annotation
- Immediate include surface: `linux/dma-mapping.h`, `linux/interrupt.h`, `linux/pci.h`, `linux/if.h`.
- Detected declarations: `struct nitrox_cmdq`, `struct nitrox_hw`, `struct nitrox_stats`, `struct nitrox_q_vector`, `struct nitrox_vfdev`, `struct nitrox_iov`, `struct nitrox_device`, `enum mcode_type`, `enum ndev_state`, `enum vf_mode`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.