drivers/crypto/cavium/nitrox/nitrox_hal.c

Source file repositories/reference/linux-study-clean/drivers/crypto/cavium/nitrox/nitrox_hal.c

File Facts

System
Linux kernel
Corpus path
drivers/crypto/cavium/nitrox/nitrox_hal.c
Extension
.c
Size
17465 bytes
Lines
680
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (se_cores) {
		case SE_MAX_CORES:
			option = "60";
			break;
		case 40:
			option = "60s";
			break;
		}
	} else if (ae_cores == (AE_MAX_CORES / 2)) {
		option = "30";
	} else {
		option = "60i";
	}

	return option;
}

static const char *get_feature_option(u8 zip_cores, int core_freq)
{
	if (zip_cores == 0)
		return "";
	else if (zip_cores < ZIP_MAX_CORES)
		return "-C15";

	if (core_freq >= 850)
		return "-C45";
	else if (core_freq >= 750)
		return "-C35";
	else if (core_freq >= 550)
		return "-C25";

	return "";
}

void nitrox_get_hwinfo(struct nitrox_device *ndev)
{
	union emu_fuse_map emu_fuse;
	union rst_boot rst_boot;
	union fus_dat1 fus_dat1;
	unsigned char name[IFNAMSIZ * 2] = {};
	int i, dead_cores;
	u64 offset;

	/* get core frequency */
	offset = RST_BOOT;
	rst_boot.value = nitrox_read_csr(ndev, offset);
	ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK;

	for (i = 0; i < NR_CLUSTERS; i++) {
		offset = EMU_FUSE_MAPX(i);
		emu_fuse.value = nitrox_read_csr(ndev, offset);
		if (emu_fuse.s.valid) {
			dead_cores = hweight32(emu_fuse.s.ae_fuse);
			ndev->hw.ae_cores += AE_CORES_PER_CLUSTER - dead_cores;
			dead_cores = hweight16(emu_fuse.s.se_fuse);
			ndev->hw.se_cores += SE_CORES_PER_CLUSTER - dead_cores;
		}
	}
	/* find zip hardware availability */
	offset = FUS_DAT1;
	fus_dat1.value = nitrox_read_csr(ndev, offset);
	if (!fus_dat1.nozip) {
		dead_cores = hweight8(fus_dat1.zip_info);
		ndev->hw.zip_cores = ZIP_MAX_CORES - dead_cores;
	}

	/* determine the partname
	 * CNN55<core option>-<freq><pincount>-<feature option>-<rev>
	 */
	snprintf(name, sizeof(name), "CNN55%s-%3dBG676%s-1.%u",
		 get_core_option(ndev->hw.se_cores, ndev->hw.ae_cores),
		 ndev->hw.freq,
		 get_feature_option(ndev->hw.zip_cores, ndev->hw.freq),
		 ndev->hw.revision_id);

	/* copy partname */
	strscpy(ndev->hw.partname, name, sizeof(ndev->hw.partname));
}

void enable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
{
	u64 value = ~0ULL;
	u64 reg_addr;

	/* Mailbox interrupt low enable set register */
	reg_addr = NPS_PKT_MBOX_INT_LO_ENA_W1S;
	nitrox_write_csr(ndev, reg_addr, value);

	/* Mailbox interrupt high enable set register */
	reg_addr = NPS_PKT_MBOX_INT_HI_ENA_W1S;

Annotation

Implementation Notes