drivers/crypto/cavium/nitrox/nitrox_isr.c
Source file repositories/reference/linux-study-clean/drivers/crypto/cavium/nitrox/nitrox_isr.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/cavium/nitrox/nitrox_isr.c- Extension
.c- Size
- 11343 bytes
- Lines
- 459
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/pci.hlinux/printk.hlinux/slab.hnitrox_dev.hnitrox_csr.hnitrox_common.hnitrox_hal.hnitrox_isr.hnitrox_mbx.h
Detected Declarations
function nps_pkt_slc_isrfunction clear_nps_core_err_intrfunction clear_nps_pkt_err_intrfunction clear_pom_err_intrfunction clear_pem_err_intrfunction clear_lbc_err_intrfunction clear_efl_err_intrfunction clear_bmi_err_intrfunction nps_core_int_taskletfunction VFfunction nitrox_unregister_interruptsfunction nitrox_register_interruptsfunction nitrox_sriov_unregister_interruptsfunction nitrox_sriov_register_interupts
Annotated Snippet
if (core_int.s.se_err) {
offset = EFL_CORE_SE_ERR_INTX(i);
value = nitrox_read_csr(ndev, offset);
nitrox_write_csr(ndev, offset, value);
}
}
}
static void clear_bmi_err_intr(struct nitrox_device *ndev)
{
u64 value;
value = nitrox_read_csr(ndev, BMI_INT);
nitrox_write_csr(ndev, BMI_INT, value);
dev_err_ratelimited(DEV(ndev), "BMI_INT 0x%016llx\n", value);
}
static void nps_core_int_tasklet(unsigned long data)
{
struct nitrox_q_vector *qvec = (void *)(uintptr_t)(data);
struct nitrox_device *ndev = qvec->ndev;
/* if pf mode do queue recovery */
if (ndev->mode == __NDEV_MODE_PF) {
} else {
/**
* if VF(s) enabled communicate the error information
* to VF(s)
*/
}
}
/*
* nps_core_int_isr - interrupt handler for NITROX errors and
* mailbox communication
*/
static irqreturn_t nps_core_int_isr(int irq, void *data)
{
struct nitrox_q_vector *qvec = data;
struct nitrox_device *ndev = qvec->ndev;
union nps_core_int_active core_int;
core_int.value = nitrox_read_csr(ndev, NPS_CORE_INT_ACTIVE);
if (core_int.s.nps_core)
clear_nps_core_err_intr(ndev);
if (core_int.s.nps_pkt)
clear_nps_pkt_err_intr(ndev);
if (core_int.s.pom)
clear_pom_err_intr(ndev);
if (core_int.s.pem)
clear_pem_err_intr(ndev);
if (core_int.s.lbc)
clear_lbc_err_intr(ndev);
if (core_int.s.efl)
clear_efl_err_intr(ndev);
if (core_int.s.bmi)
clear_bmi_err_intr(ndev);
/* Mailbox interrupt */
if (core_int.s.mbox)
nitrox_pf2vf_mbox_handler(ndev);
/* If more work callback the ISR, set resend */
core_int.s.resend = 1;
nitrox_write_csr(ndev, NPS_CORE_INT_ACTIVE, core_int.value);
return IRQ_HANDLED;
}
void nitrox_unregister_interrupts(struct nitrox_device *ndev)
{
struct pci_dev *pdev = ndev->pdev;
int i;
for (i = 0; i < ndev->num_vecs; i++) {
struct nitrox_q_vector *qvec;
int vec;
qvec = ndev->qvec + i;
if (!qvec->valid)
continue;
/* get the vector number */
Annotation
- Immediate include surface: `linux/pci.h`, `linux/printk.h`, `linux/slab.h`, `nitrox_dev.h`, `nitrox_csr.h`, `nitrox_common.h`, `nitrox_hal.h`, `nitrox_isr.h`.
- Detected declarations: `function nps_pkt_slc_isr`, `function clear_nps_core_err_intr`, `function clear_nps_pkt_err_intr`, `function clear_pom_err_intr`, `function clear_pem_err_intr`, `function clear_lbc_err_intr`, `function clear_efl_err_intr`, `function clear_bmi_err_intr`, `function nps_core_int_tasklet`, `function VF`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.