drivers/crypto/ccp/ccp-crypto-aes-galois.c
Source file repositories/reference/linux-study-clean/drivers/crypto/ccp/ccp-crypto-aes-galois.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/ccp/ccp-crypto-aes-galois.c- Extension
.c- Size
- 5926 bytes
- Lines
- 259
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/sched.hlinux/delay.hlinux/scatterlist.hlinux/string.hlinux/crypto.hcrypto/internal/aead.hcrypto/algapi.hcrypto/aes.hcrypto/ctr.hcrypto/gcm.hcrypto/scatterwalk.hccp-crypto.h
Detected Declarations
struct ccp_aes_aead_deffunction Coprocessorfunction ccp_aes_gcm_setkeyfunction ccp_aes_gcm_setauthsizefunction ccp_aes_gcm_cryptfunction ccp_aes_gcm_encryptfunction ccp_aes_gcm_decryptfunction ccp_aes_gcm_cra_initfunction ccp_aes_gcm_cra_exitfunction ccp_register_aes_aeadfunction ccp_register_aes_aeads
Annotated Snippet
struct ccp_aes_aead_def {
enum ccp_aes_mode mode;
unsigned int version;
const char *name;
const char *driver_name;
unsigned int blocksize;
unsigned int ivsize;
struct aead_alg *alg_defaults;
};
static struct ccp_aes_aead_def aes_aead_algs[] = {
{
.mode = CCP_AES_MODE_GHASH,
.version = CCP_VERSION(5, 0),
.name = "gcm(aes)",
.driver_name = "gcm-aes-ccp",
.blocksize = 1,
.ivsize = AES_BLOCK_SIZE,
.alg_defaults = &ccp_aes_gcm_defaults,
},
};
static int ccp_register_aes_aead(struct list_head *head,
const struct ccp_aes_aead_def *def)
{
struct ccp_crypto_aead *ccp_aead;
struct aead_alg *alg;
int ret;
ccp_aead = kzalloc_obj(*ccp_aead);
if (!ccp_aead)
return -ENOMEM;
INIT_LIST_HEAD(&ccp_aead->entry);
ccp_aead->mode = def->mode;
/* Copy the defaults and override as necessary */
alg = &ccp_aead->alg;
*alg = *def->alg_defaults;
strscpy(alg->base.cra_name, def->name);
strscpy(alg->base.cra_driver_name, def->driver_name);
alg->base.cra_blocksize = def->blocksize;
ret = crypto_register_aead(alg);
if (ret) {
pr_err("%s aead algorithm registration error (%d)\n",
alg->base.cra_name, ret);
kfree(ccp_aead);
return ret;
}
list_add(&ccp_aead->entry, head);
return 0;
}
int ccp_register_aes_aeads(struct list_head *head)
{
int i, ret;
unsigned int ccpversion = ccp_version();
for (i = 0; i < ARRAY_SIZE(aes_aead_algs); i++) {
if (aes_aead_algs[i].version > ccpversion)
continue;
ret = ccp_register_aes_aead(head, &aes_aead_algs[i]);
if (ret)
return ret;
}
return 0;
}
Annotation
- Immediate include surface: `linux/module.h`, `linux/sched.h`, `linux/delay.h`, `linux/scatterlist.h`, `linux/string.h`, `linux/crypto.h`, `crypto/internal/aead.h`, `crypto/algapi.h`.
- Detected declarations: `struct ccp_aes_aead_def`, `function Coprocessor`, `function ccp_aes_gcm_setkey`, `function ccp_aes_gcm_setauthsize`, `function ccp_aes_gcm_crypt`, `function ccp_aes_gcm_encrypt`, `function ccp_aes_gcm_decrypt`, `function ccp_aes_gcm_cra_init`, `function ccp_aes_gcm_cra_exit`, `function ccp_register_aes_aead`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.